MV78200 Datasheet, PDF (93/128 Pages) –

9.6.6.7
SDRAM DDR2 Interface Test Circuit
Figure 20: SDRAM DDR2 Interface Test Circuit
VDDIO/2
Test Point
50 ohm
CL
Electrical Specifications
9.6.6.8
SDRAM DDR2 Interface AC Timing Diagrams
Figure 21: SDRAM DDR2 Interface Write AC Timing Diagram
tDSH
tDSS
CLK tCH
tCL
CLKn
DQS
DQSn
tWPRE
tDQSH tDQSL
tWPST
tDIPW
DQ
tDOVB tDOVA
Figure 22: SDRAM DDR2 Interface Address and Control AC Timing Diagram
CLK tCH
tCL
CLKn
ADDRESS/
CONTROL
tIPW
tAOVB tAOVA
Copyright © 2008 Marvell
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MV-S104671-U0 Rev. C
Page 93