MV78200 Datasheet, PDF (47/128 Pages) –

Clocking
PLLs and Clock Pins
The MV78200 drives TCLK clock tree output on TCLK_OUT pin. The device can also configured to
drive a divided (1:N) TCLK on TCLK_OUT pin.
The TCLK clock tree to each of the MV78200 units can be gated via register. This is useful for power
saving modes, when most of the chip interfaces are not in use. See the Power Saving section in the
Functional Specification for further details.
A second 25 MHz input clock, CLK25_PT, is used as a reference clock for the USB PHY PLL, for the
CLK125 PLL, and for the SATA PHY PLL. This clock must be pure tone.
Note
„ If the SSC clock is not required, CLK25_PT can be configured via reset strapping
to also drive the PCLK and TCLK PLLs, as shown in Figure 3, MV78200 Clocks,
on page 46. If using this configuration, tie CLK25_SSC to VSS via a pull down
resistor.
„ The MV78200 SATA PHY generates an SSC signal on its output (TX_P/TX_N) and
tolerates an SSC signal on its input (RX_P/RX_N), as defined in the SATA
specification.
The PCI Express PHY receives a 100 MHz reference clock. It generates two clocks:
„ A 250 MHz PCLK used by the PCI Express unit (transaction layer, link layer, and PHY MAC
layer)
„ A 2.5 GHz clock for the PHY analog part.
The PCI Express PLL also tolerates a spread spectrum reference clock, as defined by the PCI
Express specification:
„ Spread of -0.5% of the maximum frequency
„ The modulation frequency does not exceed 33 kHz
Copyright © 2008 Marvell
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MV-S104671-U0 Rev. C
Page 47