MV78200 Datasheet, PDF (61/128 Pages) –

System Power Up and Reset Settings
Pins Sample Configuration
Table 28: Reset Configuration (Continued)
Pin
Power Rail
Configuration Function
DEV_A[2:1]
VDDO_C
TCLK frequency select/TCLK De-skew PLL Tune
If DEV_A[0] is set to 1 - DEV_A[2:1] functions as TCLK frequency select:
0x0 = 166 MHz
0x1 = 200 MHz
0x2, 0x3 = Reserved
If DEV_A[0] is set to 0, DEV_A[2:1] functions as TCLK de-skew PLL Tune.
A setting recommendation will be released after chip silicon testing.
When using TCLK_IN input Board design should support future pull up/pull
down requirement on these pins. A final setting recommendation will be
published following silicon samples.
NOTE: Internally pulled to 0x1.
GE0_TXD[0]
VDD_GE
TCLK De-skewer PLL Frequency Band Select
Functions as TCLK De-Skewer PLL Frequency band select. Relevant for
De-skew mode only (DEV_A[0] is set to 0) .
0 = 166 MHz
1 = 200 MHz
NOTE: Internally pulled down to 0x0.
GE0_TXD[1]
VDD_GE
Reserved
This signal must be sampled as 1 at reset de-assertion.
NOTE: Internally pulled up to 0x1.
GE0_TXD[3:2]
VDD_GE
DEV_ALE Mode Select
Defines DEV_ALE[1:0] behaviour in respect to address driven by device bus
controller (address setup and hold time in respect to DEV_ALE falling edge).
Useful for device bus topologies in which DEV_AD bus is heavily loaded.
0x0 = Address is driven for two TCLK cycles. ALE toggles after one TCLK
cycle.
0x1 = Address is driven for three TCLK cycles. ALE toggles after two TCLK
cycles.
0x2 = Address is driven for four TCLK cycles. ALE toggles after three TCLK
cycles.
0x3 = Reserved
NOTE: Internally pulled down to 0x0.
GE0_TXCTL
VDD_GE
Reserved
This signal must be sampled as 0 at reset de-assertion.
NOTE: Internally pulled down to 0x0.
Note
Even if using a 8/16-bit device, the reset sampling on the upper device bus is still used.
Copyright © 2008 Marvell
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MV-S104671-U0 Rev. C
Page 61