MV78200 Datasheet, PDF (53/128 Pages) –

System Power Up and Reset Settings
Power Up/Down Sequence Requirements
7
7.1
7.1.1
System Power Up and Reset Settings
This section provides information about the MV78200 power-up sequence and configuration at
reset.
Power Up/Down Sequence Requirements
Power Up Sequence Requirements
These guidelines must be applied to meet the MV78200 device power-up requirements:
„ The Non-Core voltages (I/O and Analog) as listed in Table 27 must reach 70% of their voltage
level before the Core voltages reach 70% of their voltage level.
The order of the power up sequence between the Non-Core voltages is unimportant so long as
the Non-Core voltages power up before the Core voltages reach 70% of their voltage level
(shown in Figure 4).
„ The reset signal(s) must be asserted before the Core voltages reach 70% of their voltage level
(shown in Figure 4).
„ The reference clock(s) inputs must toggle with their respective voltage levels before the Core
Voltages reach 70% of their voltage level (shown in Figure 4).
Table 27: I/O and Core Voltages
I/O Voltages
Non-Core Voltages
Analog Power Supplies
VDD_GE
VDD_M
VDDO_A
VDDO_B
VDDO_C
VDDO_D
PLL_AVDD
PEX0_AVDD
PEX1_AVDD
USB0_AVDD, USB1_AVDD, USB2_AVDD
SATA0_AVDD, SATA1_AVDD
Core Voltages
VDD
VDD_CPU0,
VDD_CPU1
Copyright © 2008 Marvell
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MV-S104671-U0 Rev. C
Page 53