MV78200 Datasheet, PDF (91/128 Pages) –

Electrical Specifications
9.6.6.5
SDRAM DDR2 266 MHz Interface AC Timing Table
Table 48: SDRAM DDR2 266 MHz Interface AC Timing Table
De s cr iption
Clock frequency
DQ and DM valid output time bef ore DQS transition
DQ and DM valid output time af ter DQS transition
DQ and DM output pulse w idth
DQS output high pulse w idth
DQS output low pulse w idth
DQS falling edge to CLK-CLKn rising edge
DQS f alling edge f rom CLK-CLKn rising edge
CLK-CLKn rising edge to DQS output rising edge
DQS w rite preamble
DQS w rite postamble
CLK-CLKn high-level w idth
CLK-CLKn low -level w idth
DQ input setup time relative to DQS in transition
DQ input hold time relative to DQS in transition
Address and Control valid output time before CLK-CLkn rising edge
Address and Control valid output time after CLK-CLKn rising edge
Address and control output pulse w idth
Sym bol
f CK
tDOVB
tDOVA
tDIPW
tDQSH
tDQSL
tDSS
tDSH
tDQSS
tWPRE
tWPST
tCH
tCL
tDSI
tDHI
tAOVB
tAOVA
tIPW
266 MHz @ 1.8V
M in
M ax
266.0
0.42
-
0.42
-
0.35
-
0.35
-
0.35
-
0.34
-
0.34
-
-0.11
0.11
0.35
-
0.41
-
0.45
0.55
0.45
0.55
-0.50
-
1.20
-
2.90
-
0.30
-
0.67
-
Units Notes
MHz
-
ns
-
ns
-
tCK
-
tCK
-
tCK
-
tCK
1
tCK
1
tCK
-
tCK
-
tCK
-
tCK
1
tCK
1
ns
-
ns
-
ns
1, 2
ns
1, 2
tCK
-
Note s :
General comment: All timing values w ere measured from vref to vref, unless otherw ise specified.
General comment: All input timing values assume minimum slew rate of 1 V/ns (slew rate measured f rom Vref +/-125 mV).
General comment: tCK = 1/fCK.
General comment: For all signals, the load is CL = 16 pF.
1. This timing value is defined on CLK / CLKn crossing point.
2. This timing value is defined w hen Address and Control signals are output ¼tCK after CLK-CLKn rising edge.
For more information, see register settings.
Copyright © 2008 Marvell
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MV-S104671-U0 Rev. C
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