MV78200 Datasheet, PDF (62/128 Pages) –

7.5
MV78200
Hardware Specifications
Power Up and Boot Sequence
The MV78200 requires that SYSRSTn remain asserted for at least 1 ms after power and clocks are
stable. The following procedure describes the boot sequence starting with the reset assertion:
1. While SYSRSTn is asserted, the PCLK, TCLK, and CLK125 PLLS are locked. SYSRSTn
assertion should be at least 1 ms.
2. Upon SYSRSTn de-assertion, the pad drive auto-calibration process starts. It takes 512 TCLK
cycles.
3. In parallel, TCLK de-skew PLL locks when working in de-skew mode.
4. If configured to boot from NAND Flash which does not support preload operation, the MV78200
also performs a NAND Flash boot init sequence.
Upon completing the above sequence, the CPU reset is deasserted, and CPU starts executing boot
code from DEV_BOOTCSn (whether it is a NOR Flash or a NAND Flash or from SPI Flash).
As part of the CPU boot code, the CPU typically performs the following:
„ Change the chip default address map if required, and configure PCI-Express address map.
„ Configure device bus timing parameters according to devices attached to device bus.
„ Configures the proper DRAM controller parameters, and then triggers DRAM initialization (set
DRAM Initialization Control register’s <InitEn> bit [0] to 1).
„ If using DRAM ECC, also initializes DRAM content. Initializes proper ECC to the entire DRAM
space.
„ Set the <PEXEn> bits in the CPU Control and Status register to wake up the PCI Express link.
For Dual CPU operation, CPU0 must also change the default address map of CPU1, specifiaclly the
boot window.
MV-S104671-U0 Rev. C
Page 62
Document Classification: Proprietary Information
Copyright © 2008 Marvell
December 6, 2008, Preliminary