MV78200 Datasheet, PDF (11/128 Pages) –

List of Figures
List of Figures
1 Overview........................................................................................................................................... 15
Figure 1: MV78200 Application Example ........................................................................................................16
2 Pin Information ................................................................................................................................ 17
Figure 2: MV78200 Interface Pin Logic Diagram ............................................................................................18
3 Unused Interface Strapping............................................................................................................ 41
4 MV78200 Pin Map and Pin List ....................................................................................................... 42
5 Clocking............................................................................................................................................ 43
Figure 3: MV78200 Clocks...............................................................................................................................46
6 Pin Multiplexing ............................................................................................................................... 48
7 System Power Up and Reset Settings ........................................................................................... 53
Figure 4: Power Up Sequence Example ..........................................................................................................54
8 JTAG Interface ................................................................................................................................. 63
Figure 5: MV78200 TAP Controller ..................................................................................................................63
9 Electrical Specifications (Preliminary) .......................................................................................... 64
Figure 6: TCLK_Out Reference Clock Test Circuit ..........................................................................................75
Figure 7: TCLK_Out AC Timing Diagram ........................................................................................................76
Figure 8: RGMII Test Circuit ............................................................................................................................77
Figure 9: RGMII AC Timing Diagram ...............................................................................................................78
Figure 10: MII Test Circuit..................................................................................................................................79
Figure 11: MII Output Delay AC Timing Diagram ..............................................................................................79
Figure 12: MII Input AC Timing Diagram ...........................................................................................................80
Figure 13: GMII Test Circuit ...............................................................................................................................81
Figure 14: GMII Output AC Timing Diagram ......................................................................................................82
Figure 15: GMII Input AC Timing Diagram.........................................................................................................82
Figure 16: MDIO Master Mode Test Circuit .......................................................................................................83
Figure 17: MDC Master Mode Test Circuit ........................................................................................................84
Figure 18: SMI Master Mode Output AC Timing Diagram .................................................................................84
Figure 19: SMI Master Mode Input AC Timing Diagram ....................................................................................84
Figure 20: SDRAM DDR2 Interface Test Circuit ................................................................................................93
Figure 21: SDRAM DDR2 Interface Write AC Timing Diagram .........................................................................93
Figure 22: SDRAM DDR2 Interface Address and Control AC Timing Diagram .................................................93
Figure 23: SDRAM DDR2 Interface Read AC Timing Diagram .........................................................................94
Figure 24: SPI (Master Mode) Test Circuit ........................................................................................................95
Figure 25: SPI (Master Mode) Normal Output AC Timing Diagram ...................................................................96
Copyright © 2008 Marvell
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MV-S104671-U0 Rev. C
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