MV78200 Datasheet, PDF (88/128 Pages) –

MV78200
Hardware Specifications
9.6.6.3
SDRAM DDR2 333 MHz Interface AC Timing Table
Table 45: SDRAM DDR2 333 MHz Interface AC Timing Table
333 MHz @ 1.8V
De s cr iption
Sym bol Min
Max Units Notes
Clock frequency
f CK
333.0
MHz
-
DQ and DM valid output time bef ore DQS transition
tDOVB
0.45
-
ns
-
DQ and DM valid output time af ter DQS transition
tDOVA
0.45
-
ns
-
DQ and DM output pulse w idth
tDIPW
0.35
- tCK(avg) -
DQS output high pulse w idth
tDQSH
0.35
- tCK(avg) -
DQS output low pulse w idth
tDQSL
0.35
- tCK(avg) -
DQS falling edge to CLK-CLKn rising edge
tDSS
0.34
- tCK(avg) 1
DQS f alling edge f rom CLK-CLKn rising edge
tDSH
0.34
- tCK(avg) 1
CLK-CLKn rising edge to DQS output rising edge
tDQSS -0.11
0.11 tCK(avg) -
DQS w rite preamble
tWPRE
0.35
- tCK(avg) -
DQS w rite postamble
tWPST
0.41
- tCK(avg) -
CLK-CLKn high-level w idth
tCH
0.48
0.52 tCK(avg) 1, 2, 3
CLK-CLKn low -level w idth
tCL
0.48
0.52 tCK(avg) 1, 2, 4
DQ input setup time relative to DQS in transition
tDSI
-0.50
-
ns
-
DQ input hold time relative to DQS in transition
tDHI
0.75
-
ns
-
Address and control output pulse w idth
tIPW
0.67
- tCK(avg) -
Note s :
General comment: All timing values w ere measured from vref to vref, unless otherw ise specified.
General comment: All input timing values assume minimum slew rate of 1 V/ns (slew rate measured f rom Vref +/-125 mV).
General comment: All timing parameters w ith DQS signal are defined on DQS-DQSn crossing point.
General comment: For Address and Control output timing parameters, refer to the Address Timing table.
General comment: tCK = 1/fCK.
General comment: For all signals, the load is CL = 14 pF.
1. This timing value is defined on CLK / CLKn crossing point.
2. Ref er to SDRAM DDR2 clock specif ications table f or more inf ormation.
3. tCH(avg) is defined as the average HIGH pulse w idth, as calculated across any consecutive 200 HIGH pulses.
4. tCL(avg) is defined as the average LOW pulse w idth, as calculated across any consecutive 200 LOW pulses.
MV-S104671-U0 Rev. C
Page 88
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Copyright © 2008 Marvell
December 6, 2008, Preliminary