MV78200 Datasheet, PDF (58/128 Pages) –

MV78200
Hardware Specifications
Table 28: Reset Configuration (Continued)
Pin
Power Rail
Configuration Function
DEV_AD[13:12] VDDO_C
PCLK0 to CPU0 L2 ratio
0x0 = 1
0x1 = 2
0x2 = 3
0x3 = Reserved
NOTE: Internally pulled to 0x1.
DEV_AD[17:14]
[15:14] VDDO_C
[17:16] VDDO_B
PCLK1 to HCLK ratio
0x0 = 1
0x1 = 1.5
0x2 = 2
0x3 = 2.5
0x4 = 3
0x5 = 3.5
0x6 = 4
0x7 = 4.5
0x8 = 5
0x9 = 5.5
0xA = 6
0xB–0xF = Reserved
NOTE: Internally pulled to 0x4.
DEV_AD[19:18] VDDO_B
PCLK1 to CPU1 L2 ratio
0x0 = 1
0x1 = 2
0x2 = 3
0x3 = Reserved
NOTE: Internally pulled to 0x1.
DEV_AD[20]
VDDO_B
CPU1 Enable
This signal must be sampled as 0 at reset de-assertion.
0 = Disable
1 = Enable
NOTE: Internally pulled down to 0x0.
DEV_AD[22:21] VDDO_B
DEV_BootCEn Device Width
0x0 = 8 bits
0x1 = 16 bits
0x2 = 32 bits
0x3 = Reserved
NOTE: Internally pulled down to 0x0.
MV-S104671-U0 Rev. C
Page 58
Document Classification: Proprietary Information
Copyright © 2008 Marvell
December 6, 2008, Preliminary