MV78200 Datasheet, PDF (89/128 Pages) –

Electrical Specifications
Table 46: SDRAM DDR2 333 MHz Interface Address and Control Timing Table
De s cr iption
Address and Control invalid output time before CLK-CLkn rising edge
Address and Control invalid output time after CLK-CLKn rising edge
Sym bol
tAOIB
tAOIA
333 MHz @ 1.8V
M in
M ax
-
0.28
-
0.28
Address and Control valid output time before CLK-CLkn rising edge
tAOVB 1.00
-
Address and Control valid output time after CLK-CLKn rising edge
tAOVA 1.00
-
Units
ns
ns
ns
ns
Note s
1, 3
1, 3
1, 2
1, 2
Note s :
General comment: All timing values w ere measured from vref to vref, unless otherw ise specified.
General comment: For all signals, the load is CL = 14 pF.
1. This timing value is defined on CLK / CLKn crossing point.
2. This timing value is defined w hen Address and Control signals are output on CLK-CLKn falling edge.
For more information, see register settings.
3. This timing value is defined w hen Address and Control signals are output on CLK-CLKn rising edge
(1T and 2T configurations). For more information, see register settings.
Copyright © 2008 Marvell
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MV-S104671-U0 Rev. C
Page 89