MV78200 Datasheet, PDF (60/128 Pages) –

MV78200
Hardware Specifications
Table 28: Reset Configuration (Continued)
Pin
Power Rail
Configuration Function
DEV_ALE[0]
VDDO_C
VDDO_B Voltage Select
0 = 1.8V
1 = 3.3V
NOTE: Internally pulled up to 0x1.
DEV_ALE[1]
VDDO_C
VDDO_D Voltage Select
0 = 1.8V
1 = 3.3V
NOTE: Internally pulled up to 0x1.
DEV_WEn[0]
VDDO_C
VDD_GE Voltage Select
0 = 1.8V
1 = 3.3V
NOTE: Internally pulled down to 0x0.
DEV_WEn[1]
VDDO_C
DEV_WEn and DEV_OEn multiplexing option for A[16:15] bits
Defines if OE and WE are latched at first ALE cycle as A[15] and A[16].
This fact influences the OEn and WEn signal as follows:
0 = A[16:15] bits are not multiplexed on OE and WE signals.
NOTE: Whenever CS is inactive OE and WE are inactive.
1 = A[16:15] bits are multiplexed on OE and WE signals
NOTE: Whenever CS is inactive and ALE[1:0] are high, OE and WE are
inactive.
NOTE: Internally pulled down to 0x0.
DEV_WEn[2]
VDDO_C
Reserved
This signal must be sampled as 0 at reset de-assertion.
NOTE: Internally pulled down to 0x0.
DEV_WEn[3]
VDDO_C
Reserved
This signal must be sampled as 0 at reset de-assertion.
NOTE: Internally pulled down to 0x0.
DEV_A[0]
VDDO_C
TCLK Mode Select
0 = TCLK is driven from TCLK_IN input (De-skew mode)
1 = TCLK generated internally by TCLK PLL
NOTE: Internally pulled up to 0x1.
MV-S104671-U0 Rev. C
Page 60
Document Classification: Proprietary Information
Copyright © 2008 Marvell
December 6, 2008, Preliminary