MV78200 Datasheet, PDF (46/128 Pages) –

MV78200
Hardware Specifications
The MV78200 clocking scheme is shown in Figure 3.
Figure 3: MV78200 Clocks
CLK_25_SSC
CLK25_PT
PCLK0
PCLK
PLL
HCLK
PCLK1
TCLK PLL
Sheeva^TM
Core0
DRAM
Controller
Sheeva^TM
Core1
TCLK to all of
the chip units
1:N
M_CLK_OUT[2:0]/
M_CLK_OUTn[2:0]
TCLK_OUT
de-skew
PLL
TCLK_IN
PEX_0 100 MHz HCSL
PEX_1 100 MHz HCSL
USB PHY
PLL
CLK125
(GE) PLL
SATA
PHY PLL
PCI-E
PHYs
The MV78200 supports generation of PCLK, HCLK, and TCLK from a 25 MHz input clock
CLK25_SSC. This clock can be generated by a spread spectrum clock generator (SSCG) under the
following restrictions:
„ Spread does not exceed -0.5% of the maximum frequency.
„ The modulation frequency does not exceed 33 KHz.
The PLLs using this clock source track the spread characteristics of the input clock (meaning TCLK,
PCLK, HCLK, and M_CLK_OUT also become spread spectrum clocks).
There is a single PCLK PLL that generates PCLK0 (CPU0 clock), PCLK1 (CPU1 clock) and HCLK
(CPU bus clock which is also DRAM clock). All three clocks are synchronous to each other (edge
aligned), resulting in low latency CPU to DRAM path (no synchronization required).
The CPU L2 cache clock (named XPCLK) runs relative to the CPU PCLK, with the ratio determined
by the reset configuration.
The CPU can be placed in "wait for interrupt" mode. In this mode, most of the PCLK clock tree is
turned off (only wake-up logic is kept alive).
The TCLK clock tree can be generated from one of two sources:
„ TCLK PLL (selectable 166 MHz or 200 MHz operation)
„ From external TCLK_IN input. In this mode, clock input is de-skewed to have zero skew to the
external clock input. This mode is useful when using the chip device bus as a high speed
synchronous interface (better AC timing)
MV-S104671-U0 Rev. C
Page 46
Document Classification: Proprietary Information
Copyright © 2008 Marvell
December 6, 2008, Preliminary