MV78200 Datasheet, PDF (125/128 Pages) –

Revision History
Table 69: Revision History (Continued)
Document Type
Revision
Date
Section 9.7.3, SATA Interface Electrical Characteristics
• Added Table 61, SATA I Interface Gen1m Mode Driver and Receiver Characteristics, on page 113 and Table 63,
SATA II Interface Gen2m Mode Driver and Receiver Characteristics, on page 115.
Section 10, Thermal Data (Preliminary), on page 120.
• Updated thermal data.
Section 11, Package Mechanical Dimensions, on page 121.
• Updated Figure 45, “655 Pin FCBGA Package and Dimensions in Section 11, Package Mechanical Dimensions,
on page 121. The capacitors have been removed from the figure.
Release
B
June 2, 2008
Product Overview
• Suppports 40-bit/72-bit DDR2 SDRAM interface
• Integrates four 16550-compatible UART ports; also supports DMA based transmit
• Integrates a two-channel SLIC/Codec TDM interface
• Feroceon^® core supports 32-Kbyte I-Cache and 32-Kbyte D-Cache, parity protected
• PCI Express port is PCI Express Base 1.1 compliant
Section 2, Pin Information:
• Updated the IREF_AVDD signal description in Table 3, Power Supply Pins, on page 21.
• Added thermal diode pins THERMAL_A/C and TCLK_IN note in TCLK_OUT pin in Table 4, Miscellaneous Pin
Assignments, on page 23.
• Added pullups on MPP pins
• Added M_CLKOUT[2:0] and M_CLKOUTn[2:0] in Table 5, DDR SDRAM Interface Pin Assignments, on page 25
• Revised Table 6, Device Bus Interface Pin Assignments, on page 28
• Updated Table 7, p. 30 added Table 8, PCI Express Common Pin Assignments, on page 30
• Added a note that some GbE interface pins are connected to the VDD_GE power rail and some pins are
connected to the VDDO_D power rail in Table 9, Gigabit Ethernet Port Interface Pin Assignments, on page 31.
• Added S0_AVDD and S1_AVDD as the power rail for the SATA pins in Table 11, SATA II Port 0/1 Interface Pin
Assignments, on page 35
• Changed SPI pins names in Table 13, SPI Interface Pin Assignments, on page 36.
• Updated TDM interface signals in Table 15, TDM Interface Pin Assignments, on page 38.
• Added power pins to Table 10, USB 2.0 Ports 0/1/2 Interface Pin Assignments, on page 35 and Table 15, TDM
Interface Pin Assignments, on page 38
• Changed TWSI1 from VDDO_B to VDDO_A in Table 12, TWSI Interface Pin Assignments, on page 36
Section 4, MV78100 Pin Map and Pin List
• Pinout list and map are embedded as an attachment.
• Updates are recorded in the pinout Revision History.
Section 5, Clocking
• Added TCLK:N feature
• Updated Figure 3, MV78200 Clocks, on page 46
Section 6, Pin Multiplexing
• Updated Note on page 52.
• Changed column 0x0 so that device does not wake up in default with multiple pins have same functionality (e.g.
multiple pins assigned as GPIO[0]).
• Updated UART1 muxing.
• Replaced some UA2 and UA3 flow control signals, with UA2 and UA3 data signals (column 0x3) in order to have
four UARTs even with three or four GbE ports.
• Removed UA1_TXD and UA1_RXD from multiplexing table.
• Added UA0 and UA1 CTS/RTS options on DEV_AD[31:28] (to allow for configuring four RGMII ports and still have
RGMII signals).
• Fixed GPIO muxing.
• Updated locations of SYSRST_OUTn.
• Removed SYSRST_OUTn from Dev_AD[15] and Dev_WEn[2], and put it on Dev_AD[21,24,29,30,31].
Copyright © 2008 Marvell
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MV-S104671-U0 Rev. C
Page 125