MV78200 Datasheet, PDF (124/128 Pages) –

MV78200
Hardware Specifications
13 Revision History
Table 69: Revision History
Document Type
Revision
Date
Release
C
December 6, 2008
Product Overview
• Changed the name of the Feroceon^® CPU to Sheeva^™.
Section 2, Pin Information:
• Updated the IREF_AVDD signal description Table 3, Power Supply Pins, on page 21.
• Added the SYSRST_OUTn pin to Table 4, Miscellaneous Pin Assignments, on page 23. This signal is multiplexed
on the MPP pins.
• Added the M_BB pin to Table 5, DDR SDRAM Interface Pin Assignments, on page 25. The SDRAM battery
backup signal trigger is multiplexed on the MPP pins.
• Changed the value to from 5 kilohm to 4.99 kilohm for PEXn_ISET in Table 7, PCI Express Port 0/1 Interface Pin
Assignments, on page 30.
• Added a note that some GbE interface pins are connected to the VDD_GE power rail and some pins are
connected to the VDDO_D power rail Table 9, Gigabit Ethernet Port Interface Pin Assignments, on page 31.
• Added the SATA0/1_PRESENTn and SATA0/1_ACTn pins to Table 11, SATA II Port 0/1 Interface Pin
Assignments, on page 35. These signals are multiplexed on the MPP pins.
• Added SATA0_AVDD and SATA1_AVDD as the power rail for the SATA pins in Table 11.
Section 3, Unused Interface Strapping:
• Updated pull up and pull down resistor values in Table 18, Unused Interface Strapping, on page 41.
Section 7, System Power Up and Reset Settings, on page 53.
• Added power rail information to Table 28, Reset Configuration, on page 56.
• Added 0x2 setting for DEV_AD[13:12] and DEV_AD[19:18].
• Corrected the configuration settings for DEV_AD[30] (NAND Flash Initialization Command) in Table 28 .
Section 9, Electrical Specifications (Preliminary)
• Updated the IREF_VDD to minimum -0.5V to maximum 2.2V in Table 29, Absolute Maximum Ratings, on page 64.
• Revised the IREF_VDD values and VDDO_A/B/C/D minimum and maximum values in the Table 30,
Recommended Operating Conditions, on page 66.
• Changed the embedded CPU typical power dissipation to 4200 mW in Table 31, Thermal Power Dissipation, on
page 68.
Section 9.6.6, SDRAM DDR2 Interface AC Timing
• Revised Table 43, SDRAM DDR2 400 MHz Interface Address and Control Timing Table, on page 86.
• Added Table 49, SDRAM DDR2 200 MHz Interface AC Timing Table, on page 92.
Section 9.6.7, Serial Peripheral Interface (SPI) AC Timing
• Added AC timing information for this interface.
Section 9.6.9, Device Bus Interface AC Timing
• Changed the minimum values for tAOAB from 5.0 ns to 7.5 ns and tAOAA from 5.0 ns to 3.5 ns in Table 53, Device
Bus Interface AC Timing Table (when using TCLK_OUT as the reference clock), on page 101.
Section 9.7, Differential Interface Electrical Characteristics
• Added note that the spread spectrum requirements are defined on a linear sweep or a Hershey’s kiss modulation
in Table 58, PCI Express Interface Spread Spectrum Requirements, on page 109.
MV-S104671-U0 Rev. C
Page 124
Document Classification: Proprietary Information
Copyright © 2008 Marvell
December 6, 2008, Preliminary