ISL78610 Datasheet, PDF (88/98 Pages) Intersil Corporation – Multi-Cell Li-Ion Battery Manager

ISL78610
ACCESS
Read/
Write
Read/
Write
Read/
Write
PAGE REGISTER
ADDR ADDRESS
DESCRIPTION
3’b010 6’h13 Balance Setup:
Default values are shown below, as are descriptions of each bit.
13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
BEN BSP3 BSP2 BSP1 BSP0 BWT2 BWT1 BWT0 BMD1 BMD0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BMD0, 1
Balance mode. These bits set balance mode.
BMD1 BMD0
MODE
0
0
OFF
0
1
Manual
1
0
Timed
1
1
Auto
BWT0, 1, 2
Balance wait time. Register contents are decoded to provide the required wait time
between device balancing. This is to assist with thermal management and is used with the
Auto Balance mode. See Table 16 on page 46.
BSP0, 1, 2, 3
Balance Status register pointer. Points to one of the 13 incidents of the Balance Status
register. Balance Status register 0 is used for Manual Balance mode and Timed Balance
mode. Balance status registers 1 to 12 are used for Auto Balance mode. Reads and writes
to the Balance Status register are accomplished by first configuring the Balance Status
register pointer (e.g., to read (write) Balance Status register 5, load 0101 to the Balance
Status register pointer, then read (write) to the Balance Status register). See Table 16 on
page 46.
BEN
Balance enable. Set to ‘1’ to enable balancing. ‘0’ inhibits balancing. Setting or clearing this
bit does not affect any other register contents. Balance Enable and Balance Inhibit
commands are provided to allow control of this function without requiring a register write.
These commands have the same effect as setting this bit directly. This bit is cleared
automatically when balancing is complete and the EOB bit (see “6’h19” on page 89) is set.
3’b010
6’h14
Balance Status
The Balance Status register is a multiple incidence register controlled by the BSP0-4 bits in the Balance setup
register. See Table 16 on page 46.
Bit 0 is the LSB, Bit 11 is the MSB.
13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
BAL BAL BAL BAL BAL BAL BAL BAL BAL BAL BAL BAL
12 11 10
8
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BAL1 to BAL12
Cell 1 to Cell 12 balance control, respectively. A bit set to 1 enables balance control (turns
FET on) of the corresponding cell. Writing this bit enables balance output for the current
incidence of the Balance Status register for the cells corresponding to the particular bits,
depending on the condition of BEN in the Balance Setup register. Read this bit to determine
the current status of each cell’s balance control.
3’b010 6’h15 Watchdog/Balance Time
Defaults are shown below:
13 12 11 10
9
8
7
6
5
4
3
2
1
0
BTM6 BTM5 BTM4 BTM3 BTM2 BTM1 BTM0 WDG6 WDG5 WDG4 WDG3 WDG2 WDG1 WDG0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
WDG0 to WDG6
Watchdog timeout setting. Decoded to provide the time out value for the watchdog function.
See “Watchdog Function” on page 75 for details. The watchdog may only be disabled (set
to 7’h00) if the watchdog password is set. The watchdog setting can be changed to a
nonzero value without writing to the watchdog password. Initialized to 7’h7F (128 minutes).
BTM0 to BTM6
Balance timeout setting. Decoded to provide the time out value for Timed Balance mode
and Auto Balance mode. Initialized to 7’00 (Disabled). See Table 18 on page 47.
Submit Document Feedback ₈₈
FN8830.1
June 16, 2016