ISL78610 Datasheet, PDF (64/98 Pages) Intersil Corporation – Multi-Cell Li-Ion Battery Manager

ISL78610
Response Timing Diagrams Responses are different for master, middle, and top devices. The response timings are shown in
Figures 74, 75, and 76. (Continued)
DIN
CS
SCK
DATA READY
(P2 RECEIVE)
t_CS
t_LEAD
2µs
2µs
8* t_D 8* t_D 8* t_D 8* t_D
t_LAG
t_DR:SP
(P1 TRANSMIT)
(P1 TRANSMIT)
n
(P2 RECEIVE)
(FROM DEVICE 7)
2*t_D
(P1 TRANSMIT)
N
8 * t_D
2µs
COMMAND
8* t_D 8* t_D
4* t_D
8* t_D
8* t_D
8* t_D 8* t_D 8* t_D
7*t_D (= N - n - 1)
2µs
8* t_D
8* t_D
8* t_D 8* t_D 8* t_D 8* t_D 4*t_D
Note 22
DAISY CHAIN READ DATA RESPONSE
8* t_D 8* t_D 8* t_D 8* t_D 7* t_D
DAISY CHAIN ACK RESPONSE Note 23
RESPONSE
t3
t4
t3 = t_D  50 + N – n – 1 + 4s
t4 = t_SPI  8 + t_CS + t_LEAD + t_LAG + t_DRSP + t_D  D  8 + n – 2 + 2s
Where:
t_D = Daisy chain clock period
t_SPI = SPI Clock Period
N = Stack position of top device
n = Stack position of middle stack device
t_CS = Delay imposed by host from DATA READY to the first SPI clock cycle
D = Number of bytes in the middle stack device response e.g. read all cell data = 40 bytes, Register or ACK response = 4 bytes.
NOTES:
22. Top device adds (N - n - 1) daisy clocks to allow communications to the targeted middle stack device.
23. Middle stack device adds (n - 2) daisy clocks to allow communications to the master device.
FIGURE 75. RESPONSE TIMING (MIDDLE STACK DEVICE)
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FN8830.1
June 16, 2016