ISL78610 Datasheet, PDF (86/98 Pages) Intersil Corporation – Multi-Cell Li-Ion Battery Manager

ISL78610
ACCESS
Read/
Write
Read/
Write
PAGE REGISTER
ADDR ADDRESS
DESCRIPTION
3’h010
6’h04
Fault Status:
The FAULT logic output is an OR function of the bits in this register: the output will be asserted low if any bits in the
Fault Status register are set.
13 12 11 10
9
8
7
6
5
4
3
2
1
0
MUX REG REF PAR OVSS OVBAT OW UV OV OT WDGF OSC RESERVED
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OSC
Oscillator fault bit. Bit is set in response to a fault on either the 4MHz or 32kHz oscillators.
Note that communications functions may be disrupted by a fault in the 4MHz oscillator.
WDGF
Watchdog timeout fault. Bit is set in response to a watchdog timeout.
OT
Over-temperature fault. ‘OR’ of over-temperature fault bits: TFLT0 to TFLT4. This bit is
latched. The bits in the Over-temperature Fault register must first be reset before this bit can
be reset. Reset by writing 14’h0000 to this register.
OV
Overvoltage fault. ‘OR’ of Overvoltage fault bits: OF1 to OF12. This bit is latched. The bits in
the Overvoltage Fault register must first be reset before this bit can be reset. Reset by
writing 14’h0000 to this register.
UV
Undervoltage fault. ‘OR’ of Undervoltage fault bits: UF1 to UF12. This bit is latched. The bits
in the Undervoltage Fault register must first be reset before this bit can be reset. Reset by
writing 14’h0000 to this register.
OW
Open-Wire fault. ‘OR’ of open-wire fault bits: OC0 to OC12. This bit is latched. The bits in the
Open-Wire Fault register must first be reset before this bit can be reset. Reset by writing
14’h0000 to this register.
OV_BAT
Open-wire fault on VBAT connection. Bit set to 1 when a fault is detected. May be reset via
register write (14’h0000).
OVSS
Open-wire fault on VSS connection. Bit set to 1 when a fault is detected. May be reset via
register write (14’h0000).
PAR
Register checksum (Parity) error. This bit is set in response to a register checksum error. The
checksum is calculated and stored in response to a Calc Register Checksum command and
acts on the contents of all page 2 registers. The Check Register Checksum command is
used to repeat the calculation and compare the results to the stored value. The PAR bit is
then set if the two results are not equal. This bit is not set in response to a nonvolatile
EEPROM memory checksum error. See table on page 93.
REF
Voltage reference fault. This bit is set if the voltage reference value is outside its
“power-good” range.
REG
Voltage regulator fault. This bit is set if a voltage regulator value (V3P3, VCC or V2P5) is
outside its “power-good” range.
MUX
Temperature multiplexer error. This bit is set if the VCC loopback check returns a fault. The
VCC loopback check is performed at the end of each temperature scan.
3’h010 6’h05 Cell Setup:
Default values are shown below, as are descriptions of each bit.
13 12 11 10
9
8
7
6
5
4
3
2
1
0
FFSN FFSP C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C1 to C12
Enable/disable cell overvoltage, undervoltage and open-wire detection on cells 1 to 12,
respectively. Set to 1 to disable OV/UV and open-wire tests.
FFSP
Force ADC input to Full Scale Positive. All cell scan readings forced to 14'h1FFF. All
temperature scan readings forced to 14'h3FFF.
FFSN
Force ADC input to Full Scale Negative. All cell scan readings forced to 14'h2000. All
temperature scan readings forced to 14'h0000.
NOTE: The ADC input functions normally if both FFSN and FFSP are set to '1' but this setting is not supported.
Submit Document Feedback ₈₆
FN8830.1
June 16, 2016