ISL78610 Datasheet, PDF (63/98 Pages) Intersil Corporation – Multi-Cell Li-Ion Battery Manager

ISL78610
Response Timing Diagrams Responses are different for master, middle, and top devices. The response timings are shown in
Figures 74, 75, and 76.
DIN
CS
SCK
DATA READY
(P2 RECEIVE)
t_CS
2µs
8* t_D
8* t_D
8* t_D
2µs
8* t_D
8* t_D
t_DR:SP
t_DR:WAIT
t_LAG
t_LEAD
(P1 TRANSMIT)
(P1 TRANSMIT)
(P1 TRANSMIT)
2*t_D
8 * t_D
2µs
8* t_D 8* t_D 8* t_D 8* t_D
4 * t_D
8* t_D 8* t_D 8* t_D 8* t_D
4*t_D
8 * t_D
8* t_D 8* t_D 8* t_D 8* t_D 12 * t_D
DAISY CHAIN ACK RESPONSE
t2
t2 = 8  t_SPI + t_DRSP + t_DRWAIT + t_CS + t_LEAD + t_LAG  D – t_DRSP + t_D  42 + N – 2 + 8 + 4s
Where:
t_SPI = SPI clock period
t_D = Daisy chain clock period
t_CS = Host delay from DATA READY Low to the CS Low
t_DRSP = CS High to DATA READY High
t_DRWAIT = DATA READY High time
t_LEAD = CS Low to first SPI Clock
t_LAG = Last SPI clock CS High
N = Stack position of top device
D = Number of data bytes
D = 4 for one register read (or ACK/NAK response)
D = 40 for read all voltages
D = 22 for read all temperatures
D = 22 for read all faults
D = 43 for read all setup
FIGURE 74. RESPONSE TIMING (MASTER DEVICE)
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FN8830.1
June 16, 2016