ISL78610 Datasheet, PDF (52/98 Pages) Intersil Corporation – Multi-Cell Li-Ion Battery Manager

ISL78610
Communications
All communications are conducted through the SPI port in single
8-bit byte increments. The MSB is transmitted first and the LSB is
transmitted last.
Maximum operating data rates are 2Mbps for the SPI interface.
When using the daisy chain communications system it is
recommended that the synchronous communications data rate
be at least twice that of the daisy chain system. (See Table 4.)
In stand-alone applications (non-daisy chain) data is sent without
additional address information. This maximizes the throughput
for full duplex SPI operation.
In daisy chain applications all measurement data is sent with the
corresponding device stack address (the position within the daisy
chain), parameter identifier and data address. Daisy chain
communication throughput is maximized by allowing streamed
data (accessed by a “read all data” address).
SPI Interface
The ISL78610 operates as an SPI slave capable of bus speeds up
to 2Mbps. Four lines make up the SPI interface: SCLK, DIN, DOUT
and CS. The SPI interface operates in either full duplex or half
duplex mode depending on the daisy chain status of the part.
The DOUT line is normally tri-stated (high impedance) to allow
use in a multidrop bus. DOUT is only active when CS is low.
An additional output DATA READY is used in the daisy chain
configuration to notify the host microcontroller that responses
have been received from a device in the chain.
FULL DUPLEX (STAND-ALONE) SPI OPERATION
In non-daisy chain applications, the SPI bus operates as a
standard, full duplex, SPI port. Read and write commands are
sent to the ISL78610 in 8-bit blocks. CS is taken high between
each block.
Data flow is controlled by interpreting the first bit of each
transaction and counting the requisite number of bytes. It is the
responsibility of the host microcontroller to ensure that
commands are correctly formulated, as an incorrect formulation,
(e.g., read bit instead of write bit), would cause the port to lose
synchronization.
There is a timeout period associated with the CS inactive (high)
condition, which resets all the communications counters. This
effectively resets the SPI port to a known starting condition. If CS
stays high for more than 100µs then the SPI state machine
resets.
A pending device response from a previous command is sent by
the ISL78610 during the first 2 bytes of the 3-byte Write
transaction. The third byte from the ISL78610 is then discarded
by the host microcontroller. This maintains sequencing during
3-byte (Write) transactions.
Interface timing for full duplex SPI transfers are shown in Figure
3 on page 14.
HALF DUPLEX (DAISY CHAIN) OPERATION
The SPI operates in half duplex mode when configured as a daisy
chain application (see Table 3 on page 26). Data flow is
controlled by a handshake system using the DATA READY and CS
signals. DATA READY is controlled by the ISL78610. CS is
controlled by the host microcontroller. This handshake
accommodates the delay between command receipt and device
response due to the latency of the daisy chain communications
system.
There is a timeout period associated with the CS inactive (high)
condition which resets all the communications counters. This
effectively resets the SPI port to a known starting condition. If CS
stays high for more than 100µs then the SPI state machine resets.
Responses from stack devices are received by the stack master
(stack bottom device). The stack master then asserts its DATA
READY output once the first full data byte is available. The host
microcontroller responds by asserting CS and clocking the data
out of the DOUT port. The DATA READY line is then cleared and
DOUT is tri-stated in response to CS being taken high. In this
mode the DIN and DOUT lines may be connected externally.
Half duplex communications are conducted using the DATA
READY/CS handshake as follows:
1. The host microcontroller sends a command to the ISL78610
using the CS line to select the ISL78610 and clocking data
into the ISL78610 DIN pin.
2. The ISL78610 asserts DATA READY low when it is ready to
send data to the host microcontroller. When DATA READY is
low, the ISL78610 is in transmit mode and will ignore any
data on DIN.
3. The host microcontroller asserts CS low and clocks 8 bits of
data out of DOUT using SCLK.
4. The host microcontroller then raises CS. The ISL78610
responds by raising DATA READY and tri-stating DOUT.
5. The ISL78610 reasserts DATA READY for the next byte, and so
on.
The host microcontroller must service the ISL78610 if DATA
READY is low before sending further commands. Any data sent to
DIN while DATA READY is low is ignored by the ISL78610.
A 4-byte data buffer is provided for SPI communications. This
accommodates all single transaction responses. Multiple
responses, such as those that may be produced by a device
detecting an error, would overflow this buffer. It is important
therefore that the host microcontroller reads the first byte of data
before a fifth byte arrives on the master device’s daisy chain port
so as not to risk losing data.
The DATA READY output from the ISL78610 is not asserted if CS
is already asserted. It is possible for the microcontroller to
interrupt a sequential data transfer by asserting CS before the
ISL78610 asserts DATA READY. This causes a conflict with the
communications and is not recommended. A conflict created in
this manner would be recognized by the microcontroller either
not receiving the expected response or receiving a
communications failure notification.
Interface timing for half duplex SPI transfers are shown in Figure
4 on page 14.
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FN8830.1
June 16, 2016