ISL78610 Datasheet, PDF (82/98 Pages) Intersil Corporation – Multi-Cell Li-Ion Battery Manager

ISL78610
BSP = 0010 (Balance status pointer = 2)
TABLE 67. BALANCE SETUP REGISTER
R/W PAGE ADDRESS
DATA
1
010
010011
XX XXX0 010X XXXX
X = don’t care
Step 4E. Write Balance Status register: Set bits 3, 6, 9 and 12
BAL12:1 = 1001 0010 0100
BALANCE STATUS REGISTER
R/W PAGE ADDRESS
DATA
1
010
010100
XX 1001 0010 0100
Step 4F. Write Balance Setup register: Set Balance Status
Pointer = 3
BSP = 0011 (Balance status pointer = 3)
BALANCE SETUP REGISTER
R/W PAGE ADDRESS
DATA
1
010
010011
XX XXX0 011X XXXX
X = don’t care
Step 4G. Write Balance Status register: Set bits 2, 5, 8 and 11
BAL12:1 = 0100 1001 0010
BALANCE STATUS REGISTER
R/W PAGE ADDRESS
DATA
1
010
010100
XX 0100 1001 0010
Step 4H. Write Balance Setup register: Set Balance Status
Pointer = 4
BSP = 0100 (Balance status pointer = 4)
BALANCE SETUP REGISTER
R/W PAGE ADDRESS
DATA
1
010
010011
XX XXX0 100X XXXX
X = don’t care
Step 4I. Write Balance Status register: Set bits to all zero to set
the end point for the instances.
BAL12:1 = 0000 0000 0000
BALANCE STATUS REGISTER
R/W PAGE ADDRESS
DATA
1
010
010100
XX 0000 0000 0000
Step 5. Enable balancing using Balance Enable command
BALANCE ENABLE COMMAND
R/W PAGE ADDRESS
DATA
0
011 010000
00 0000
Or enable balancing by setting BEN directly in the Balance Setup
register:
BEN = 1
BALANCE SETUP REGISTER
R/W PAGE ADDRESS
DATA
1
010
010011
XX XX1X XXXX XXXX
The balance FETs cycle through each instance of the Balance
Status register in a loop, interposing the balance wait time
between each instance. The measured voltage of each cell being
balanced is subtracted from the balance value for that cell at the
end of each Balance Status instance. The process continues until
the Balance Value register for each cell contains zero.
System Registers
System registers contain 14 bits each. All register locations are
memory mapped using a 9-bit address. The MSBs of the address
form a 3-bit page address. Page 1 (3’b001) registers are the
measurement result registers for cell voltages and temperatures.
Page 3 (3’b011) is used for commands. Pages 1 and 3 are not
subject to the checksum calculations. Page addresses 4 and 5
(3’b100 and 3b’101), with the exception of the EEPROM
checksum registers, are reserved for internal functions.
All page 2 registers (device configuration registers), together with
the EEPROM checksum registers, are subject to a checksum
calculation. The checksum is calculated in response to the
Calculate Register Checksum command using a Multiple Input
Shift Register (MISR) error detection technique. The checksum is
tested in response to a Check Register Checksum command. The
occurrence of a checksum error sets the PAR bit in the Fault
Status register and causes a Fault response accordingly. The
normal response to a PAR error is for the host microcontroller to
rewrite the page 2 register contents. A PAR fault also causes the
device to cease any scanning or cell balancing activity.
A description of each register is included in “Register
Descriptions” and includes a depiction of the register with bit
names and initialization values at power up, when the EN pin is
toggled and the device receives a Reset Command, or when the
device is reset. Bits which reflect the state of external pins are
notated “Pin” in the initialization space. Bits which reflect the
state of nonvolatile memory bits (EEPROM) are notated “NV” in
the initialization space. Initialization values are shown below
each bit name.
Reserved bits (indicated by gray areas) should be ignored when
reading and should be set to “0” when writing to them.
Submit Document Feedback ₈₂
FN8830.1
June 16, 2016