ISL78610 Datasheet, PDF (14/98 Pages) Intersil Corporation – Multi-Cell Li-Ion Battery Manager

Timing Diagrams
ISL78610
CS
(FROM µC)
t_LEAD
t_HIGH
t_LOW
t_LAG
t_SPI:TO
t_CS:WAIT
SCLK
(FROM µC)
t_A
t_V
t_F
t_HO
t_DIS
DOUT
(TO µC)
t_SU
t_HI
t_R
DIN
(FROM µC)
CLOCK DATA INTO
ISL78610
CLOCK DATA OUT OF
ISL78610
FIGURE 3. SPI FULL DUPLEX (4-WIRE) INTERFACE TIMING
CS
(FROM µC)
DATA READY
(TO µC)
SCLK
(FROM µC)
DOUT
(TO µC)
DIN
(FROM µC)
CLOCK DATA INTO
ISL78610
t_DR:SP
t_CS:WAIT
t_SPI:TO
t_DR:WAIT
t_A
t_DIS
CLOCK DATA OUT OF
ISL78610
SIGNALS ON DIN IGNORED
WHILE DATA READY IS LOW
FIGURE 4. SPI HALF DUPLEX (3-WIRE) INTERFACE TIMING
Submit Document Feedback ₁₄
FN8830.1
June 16, 2016