ISL78610 Datasheet, PDF (45/98 Pages) Intersil Corporation – Multi-Cell Li-Ion Battery Manager

ISL78610
The master device passes the ACK on to the host microcontroller
to complete the Wake-up sequence. The total time required to
wake up a complete stack of devices is dependent on the
number of devices in the stack. Table 14 gives the maximum
time from Wake-up command transmission to receipt of ACK
response (DATA READY asserted low) for stacks of 8 devices and
14 devices at various daisy chain data rates (interpolate linearly
for different number of devices).
TABLE 14. MAXIMUM WAKE-UP TIMES FOR STACKS OF 8 DEVICES
AND 14 DEVICES (WAKE-UP COMMAND TO ACK
RESPONSE)
MAXIMUM WAKE-UP TIMES
DAISY CHAIN DATA RATE (kHz) 500 250 125 62.5
Stack of 8 Devices (ms)
63
63
63
63
Stack of 14 Devices (ms)
100 100 100
100
There is no additional checking for communications faults while
devices are waking up. A communications fault is indicated by
the host microcontroller not receiving an ACK response within
the expected time.
Reset Command
All digital registers can be reset to their power-up condition using
the Reset Command.
Daisy chain devices must be reset in sequence from top stack
device to stack bottom (master) device. Sending the Reset
command to all devices using the Address All stack address has
no effect. There is no response from the stack when sending a
Reset command.
All stack address and stack size information is set to zero in
response to a Reset command. Once all devices have been reset
it is necessary to reprogram the stack address and stack size
information using the Identify command.
A Reset command should be issued following a “hard reset” in
which the EN pin is toggled.
Balance Enable Command
The Balance Enable command sets the BEN bit, which starts the
balancing operation. However, before this command becomes
operational and before balancing can commence, the balance
operation needs to be specified. See “Cell Balancing Functions”.
The Balance Enable command can be sent to all devices with one
command using Address All addressing.
Balance Inhibit Command
The Balance Inhibit command clears the BEN bit, which stops the
balancing operation. The Balance Inhibit command can be sent
to all devices with one command using Address All addressing.
CELL BALANCING FUNCTIONS
Cell balancing is performed using external MOSFETs and external
current balancing resistors (see Figure 51 on page 31). Each
MOSFET is controlled independently by the CB1 to CB12 pins of
the ISL78610. The CB1 to CB12 outputs are controlled either
directly, or indirectly by an external microcontroller through bits
in various control registers.
There are three cell balance modes, Manual, Timed and Auto.
TABLE 15. REGISTERS CONTROLLING BALANCE
REGISTER
BALANCE MODE
REFERENCE
Balance Setup
Manual, Timed, Auto Table 16 on page 46
Balance Status
Manual, Timed, Auto Table 16 on page 46
Watchdog/Balance Time Timed, Auto
Table 18 on page 47
Device Setup
Timed, Auto
“Set-Up Registers” on
page 87
Balance Value
Auto only
Table 19 on page 49
BALANCE MODE
Set the Balance mode with the BMD1 and BMD0 bits in the
Balance Setup Register (see Table 16).
In Manual mode, the host microcontroller directly controls the
state of each MOSFET output.
In Timed mode, the host microcontroller programs a balance
duration value and selects which cells are to be balanced, then
starts the balance operation. The ISL78610 turns all the FETs off
when the balance duration has been reached.
In Auto Balance mode, the host microcontroller programs the
ISL78610 to control the balance MOSFETs to remove a
programmed “charge delta” value from each cell. The ISL78610
does this by controlling the amount of charge removed from each
cell over a number of cycles, rather than trying to balance all
cells to a specific voltage.
BALANCE WAIT TIME
The balance wait time is the interval between balancing
operations in Auto Balance mode (see Table 16).
BALANCE ENABLE
When all of the other balance control bits are properly set,
setting the balance Enable bit to “1” starts the balance
operation. The BEN bit can be set by writing directly to the
Balance Setup register or by sending a Balance Enable
command. See Table 16.
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FN8830.1
June 16, 2016