ISL78610 Datasheet, PDF (25/98 Pages) Intersil Corporation – Multi-Cell Li-Ion Battery Manager

ISL78610
The gate of the N-channel MOSFET (cell locations 1 through 9)
and P-channel MOSFETs (cells 10 through 12) are normally
protected against excessive voltages during cell voltage
transients by the action of the parasitic Cgs and Cgd
capacitances. These momentarily turn on the FET in the event of
a large transient, thus limiting the Vgs values to reasonable
levels. A 10nF capacitor is included between the MOSFET gate
and source terminals to protect against EMI effects. This
capacitor provides a low impedance path to ground at high
frequencies and prevents the MOSFET turning on in response to
high frequency interference.
The 10k and 330k resistors are chosen to prevent the 9V clamp
at the output from the ISL78610 from activating.
Reduced cell counts for fewer than 12 cells are accommodated
by removing connections to the cells in the middle of the stack
first. The top and bottom cell locations are always occupied. See
“Operating with Reduced Cell Counts” on page 30 for suggested
cell configurations when using fewer than 12 cells.
CELL VOLTAGE MEASUREMENTS DURING BALANCING
The standard cell balancing circuit (Figures 41 and 43 on
page 24 and Figure 51 on page 31) is configured so the cell
measurement is taken from the drain connection of the
balancing MOSFET. When balancing is enabled for a cell, the
resulting cell measurement is then the voltage across the
balancing MOSFET (VGS voltage). This system provides a
diagnostic function for the cell balancing circuit. The input
voltage of the cell adjacent to the MOSFET drain connection is
also affected by this mechanism: the input voltage for this cell
increases by the same amount that the voltage of the balance
cell decreases.
For example, if cells 2 and 3 are both at 3.6V, and balancing is
enabled for cell 2. The voltage across the balancing MOSFET may
be only 50mV. In this case, the input voltage on the VC2 pin
would be VC1 + 50mV and cell 3 would be VC2 + 7.15V. The VC3
value in this case is outside the measurement range of the cell
input. VC3 would then read full scale voltage, which is 4.9994V.
This full scale voltage reading will occur if the sum of the
voltages on the two adjacent cells is greater than the total of 5V
plus the “balancing on” voltage of the balanced cell. Table 2
shows the cell affected when each cell is balanced.
The cell voltage measurement is affected by impedances in the
cell connectors and any associated wiring. The balance current
passes through the connections at the top and bottom of the
balanced cell. This effect further reduces the voltage measured
on the balanced cell and also increases the voltage measured on
cells above and below the balanced cell. For example, if cell 4 is
balanced with 100mA, and the total impedance of the connector
and wiring for each cell connection is 0.1Ω, then cell 4 would
read low by an additional 20mV (10mV due to each pin) while
cells 3 and 5 would both read high by 10mV.
TABLE 2. CELL READINGS DURING BALANCING
CELL WITH LOW
CELL BALANCED
READING
CELL WITH HIGH READING
1
1
2
2
2
3
3
3
4
4
4
5
5
5
6
6
6
7
7
7
8
8
8
9
9
9*
10*
10
10*
9*
11
11
10
12
12
11
NOTE: *Cells 9 and 10 produce a different result from the other cells.
Cell 9 uses an N-channel MOSFET while cell 10 uses a P-channel MOSFET.
The circuit arrangement used with these devices produces approximately
half the normal cell voltage when balancing is enabled. The adjacent cell
then sees an increase of half the voltage of the balanced cell.
Power Supplies and Reference
VOLTAGE REGULATORS
The two VBAT pins, along with V3P3, VCC and VDDEXT are used
to supply power to the ISL78610. Power for the high voltage
circuits and Sleep mode internal regulators is provided via the
VBAT pins. V3P3 is used to supply the logic circuits and VCC is
similarly used to supply the low voltage analog circuits. The V3P3
and VCC pins must not be connected to external circuits other
than those associated with the ISL78610 main voltage regulator.
The VDDEXT pin is provided for use with external circuits.
The ISL78610 main low voltage regulator uses an external NPN
pass transistor to supply 3.3V power for the V3P3 and VCC pins.
This regulator is enabled whenever the ISL78610 is in Normal
mode and may also be used to power external circuits via the
VDDEXT pin. An internal switch connects the VDDEXT pin to the
V3P3 pin. Both the main regulator and the switch are off when the
part is placed in Sleep mode or Shutdown mode (EN pin LOW.) The
pass transistor’s base is connected to the ISL78610 BASE pin. A
suitable configuration for the external components associated
with the V3P3, VCC and VDDEXT pins is shown in Figure 45.
The external pass transistor is required. Do not allow the BASE
pin to float.
VOLTAGE REFERENCE
A bypass capacitor is required between REF (pin 33) and the
analog ground VSS. The total value of this capacitor should be in
the range of 2.0µF to 2.5µF. Use X7R type dielectric capacitors
for this function. The ISL78610 continuously performs a
power-good check on the REF pin voltage starting 20ms after a
power-up, Enable or Wake-up condition. If the REF capacitor is
too large, then the reference voltage may not reach its target
voltage range before the power-good check starts and result in a
REF fault. If the capacitor is too small, then it may lead to
inaccurate voltage readings.
Submit Document Feedback ₂₅
FN8830.1
June 16, 2016