ISL78610 Datasheet, PDF (73/98 Pages) Intersil Corporation – Multi-Cell Li-Ion Battery Manager

ISL78610
TABLE 43. FAULT SETUP REGISTER
REGISTER BITS
12 11 10 9
8
765
4
3210
INTERNAL
TOTALIZER
TST4 TST3 TST2 TST1 ENABLE TST0 TEMP TOT2 TOT1 TOT0 COUNT WSCN
SCAN WIRES
SCAN
INTERVAL
SCN1 SCN0 SCN1 SCN0 TIME (ms)
0 0 0 0 None 0 Disable 0 0 0
1
0 Track Voltage Scan 0 0 0 0
16
x x x 1 ExT1 1 Enable 0 0 1
2
1 Track Temp Scan 0 0 0 1
32
x x 1 x ExT2
010
4
0010
64
x 1 x x ExT3
011
8
0011
128
1 x x x ExT4
100
16
0100
256
101
32
0101
512
110
64
0110
1024
111
128
0 1 1 1 2048
1 0 0 0 4096
1001
8192
1 0 1 0 16384
1 0 1 1 32768
1 1 0 0 65536
Diagnostic Activity Settling Time
The majority of diagnostic functions within the ISL78610 do not
affect other system activity and there is no requirement to wait
before conducting further measurements. The exceptions to this
are the open-wire test and cell balancing functions.
OPEN-WIRE TEST
The open-wire test loads each VCn pin in turn with 150µA or 1mA
current. This disturbs the cell voltage measurement while the
test is being applied e.g., a 1mA test current applied with an
input path resistance of 1kΩ reduces the pin voltage by 1V. The
time required for the cell voltage to settle following the open-wire
test is dependent on the time constant of components used in
the cell input circuit. The standard input circuit (Figure 51 on
page 31) with the components given in Table 8 on page 38
provide settling to within 0.1mV in approximately 2.8ms. This
time should be added at the end of each open-wire scan to allow
the cell voltages to settle.
CELL BALANCING
The standard applications circuit (Figure 51 on page 31)
configures the balancing circuits so that the cell input
measurement reads close to zero volts when balancing is
activated. There are time constants associated with the turn-on
and turn-off characteristics of the cell balancing system that
must be allowed for when conducting cell voltage
measurements.
The turn-on time of the balancing circuit is primarily a function of
the 25µA drive current of the cell balancing output and the gate
charge characteristic of the MOSFET and needs to be determined
for a particular setup. Turn-on settling times to within 2mV of
final “on” value are typically less than 5ms.
The turn-off time is a function of the MOSFET gate charge and
the VGS connected resistor and capacitor values (for example
R₂₇ and C₂₇ in Figure 51 on page 31) and is generally longer
than the turn-on time. As with the turn-on case, the turn-off time
needs to be determined for the particular components used.
Turn-off settling times in the range 10ms to 15ms are typical for
settling to within 0.1mV of final value.
Memory Checksum
There are two checksum operations available to the host
microcontroller for checking memory integrity, one for the
EEPROM and one for the Page 2 registers.
Two registers are provided to verify the contents of EEPROM
memory. One (Page 4, address 6’h3F) contains the correct
checksum value, which is calculated during factory testing at
Intersil. The other (Page 5, address 6’h00) contains the
checksum value calculated each time the nonvolatile memory is
loaded to shadow registers, either after a power cycle or after a
device reset. An inequality between these two numbers indicates
corruption of the shadow register contents (and possible
corruption of EEPROM data). The external microcontroller needs
to compare the two registers, since it is not automatic. Resetting
the device (using the Reset command) reloads the shadow
registers. A persistent difference between these two register
values indicates EEPROM corruption.
All Page 2 registers (device configuration registers) are subject to
a checksum calculation. A Calculate Register Checksum
command calculates the Page 2 checksum and saves the value
internally (it is not accessible). The Calculate Register Checksum
command may be run any time, but should be sent whenever a
Page 2 register is changed.
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FN8830.1
June 16, 2016