ISL78610 Datasheet, PDF (12/98 Pages) Intersil Corporation – Multi-Cell Li-Ion Battery Manager

ISL78610
Electrical Specifications V_BAT = 6 to 60V, T_A = -20°C to +85°C, unless otherwise specified. Biasing setup as in
Figure 45 on page 26 or equivalent. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 8) TYP
Open VC1 Detection Threshold
Primary Detection Threshold, VC2 to
VC12
Secondary Detection Threshold, VC2 to
VC12
Open V_BAT Fault Detection Threshold
Open VSS Fault Detection Threshold
Cell Balance Output Specifications
V_VC1
V_{VC2_12P}
V_{VC2_12S}
V_VBO
V_VSSO
CELL1 positive terminal (with respect to VSS)
V_BAT = 39.6V (Note 9)
V(VC(n - 1))-V(VCn), n = 2 to 12
V_BAT = 39.6V (Note 9)
Via ADC. VC2 to VC12 only
V_BAT = 39.6V (Note 9)
VC12 - V_BAT
VSS - VC0
0.6
0.7
-2
-1.5
-100
-30
200
250
Cell Balance Pin Output Impedance
R_CBL
CBn output off impedance
between CB(n) to VC(n-1): cells 1 to 9 and
between CB(n) to VC(n): cells 10 to 12
2
4
Cell Balance Output Current
I_CBH1
CBn output on. (CB1-CB9); V_BAT = 39.6V;
device sinking current
-28
-25
I_CBH2
CBn output on. (CB10-CB12); V_BAT = 39.6V;
device sourcing current
21
25
Cell Balance Output Leakage in
Shutdown
I_CBSD EN = GND. V_BAT = 39.6V
-500
10
External Cell Balance FET Gate Voltage
VGS CBn Output on;
External 320kΩ between VCn and CBn
(n = 10 to 12) and between CBn and VCn-1
(n = 1 to 9)
7.04
8.00
Internal Cell Balance Output Clamp
VCBCL I_CB = 100µA
8.94
Logic Inputs: SCLK, CS, DIN
Low Level Input Voltage
VIL
High Level Input Voltage
VIH
1.75
Input Hysteresis
VHYS
250
Input Current
IIN
0V < V_IN < V3P3
-1
Input Capacitance (Note 9)
CIN
Logic Inputs: EN, COMMS SELECT1, COMMS SELECT2, COMMS RATE 0, COMMS RATE 1
Low Level Input Voltage
VIL
High Level Input Voltage
VIH
0.7*V3P3
Input Hysteresis
VHYS (Note 9)
0.05*V3P3
Input Current
IIN
0V < V_IN < V3P3
-1
Input Capacitance (Note 9)
CIN
Logic Outputs: DOUT, FAULT, DATA READY
Low Level Output Voltage
VOL1 At 3mA sink current
0
VOL2 At 6mA sink current
0
High Level Output Voltage
VOH1 At 3mA source current
V3P3 – 0.4
VOH2 At 6mA source current
V3P3 – 0.6
SPI Interface Timing See Figures 3 and 4
SCLK Clock Frequency
f_SCLK
Pulse Width of Input Spikes Suppressed
t_IN1
50
MAX
(Note 8)
0.8
0
50
5
-21
28
700
8.96
0.8
+1
10
0.3*V3P3
+1
10
0.4
0.6
V3P3
V3P3
2
200
UNIT
V
V
mV
mV
mV
MΩ
μA
μA
nA
V
V
V
V
mV
µA
pF
V
V
V
µA
pF
V
V
V
V
MHz
ns
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FN8830.1
June 16, 2016