ISL78610 Datasheet, PDF (13/98 Pages) Intersil Corporation – Multi-Cell Li-Ion Battery Manager

ISL78610
Electrical Specifications V_BAT = 6 to 60V, T_A = -20°C to +85°C, unless otherwise specified. Biasing setup as in
Figure 45 on page 26 or equivalent. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 8)
MAX
TYP (Note 8) UNIT
Enable Lead Time
Clock High Time
Clock Low Time
Enable Lag Time
Slave Access Time
Data Valid Time
Data Output Hold Time
DOUT Disable Time
Data Setup Time
Data Input Hold Time
t_LEAD Chip select low to ready to receive clock data
200
t_HIGH
200
t_LOW
200
t_LAG
Last data read clock edge to Chip Select high
250
t_A
Chip Select low to DOUT active
t_V
Clock low to DOUT valid
t_HO
Data hold time after falling edge of SCLK
0
t_DIS
DOUT disabled following rising edge of CS
t_SU
Data input valid prior to rising edge of SCLK
100
t_HI
Data input to remain valid following rising edge of
80
SCLK
ns
ns
ns
ns
200
ns
350
ns
ns
240
ns
ns
ns
Data Ready Start Delay Time
t_DR:ST Minimum chip select high to Data Ready low
100
ns
Data Ready Stop Delay Time
t_DR:SP Maximum chip select high to Data Ready high
750
ns
Data Ready High Time
t_DR:WAIT Minimum time between bytes
1.0
µs
Chip Select High Time
t_CS:WAIT Minimum high time for CS between bytes
200
ns
SPI Communications Timeout
t_SPI:TO Maximum time the CS remains high before SPI
100
µs
communications time out - requiring the start of a new
command
DOUT Rise Time
t_R
Up to 50pF load
DOUT Fall Time
t_F
Up to 50pF load
Daisy Chain Communications Interface: DHi1, DLo1, DHi2, DLo2
30
ns
30
ns
Daisy Chain Clock Frequency
Comms Rate (0, 1) = 11
450
500
550
kHz
Comms Rate (0, 1) = 10
225
250
275
kHz
Comms Rate (0, 1) = 01
112.5
125 137.5
kHz
Comms Rate (0, 1) = 00
56.25 62.5 68.75
kHz
Common-Mode Reference Voltage
V_BAT/2
V
NOTES:
8. Compliance to data sheet limits is assured by one or more methods: production test, characterization and/or design. Limits are 100% tested, unless
declared otherwise.
9. These MIN and/or MAX values are based on characterization data and are not 100% tested.
10. Stresses may be induced in the ISL78610 during soldering or other high temperature events that affect measurement accuracy. Initial accuracy does
not include effects due to this. See Figure 8 for cell reading accuracy obtained after soldering to Intersil evaluation boards. When soldering the
ISL78610 to a customized circuit board with a layout or construction significantly differing from the Intersil evaluation board, design verification tests
should be applied to determine drift due to soldering and over lifetime.
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FN8830.1
June 16, 2016