ISL78610 Datasheet, PDF (65/98 Pages) Intersil Corporation – Multi-Cell Li-Ion Battery Manager

ISL78610
Response Timing Diagrams Responses are different for master, middle, and top devices. The response timings are shown in
Figures 74, 75, and 76. (Continued)
DIN
CS
SCK
DATA READY
t_CS
t_LEAD
t_DR:SP
t_LAG
(P2 RECEIVE)
2µs
8* t_D
8* t_D
8* t_D
2µs
8* t_D
(P1 TRANSMIT)
(P1 TRANSMIT)
8* t_D 8* t_D 8* t_D 8* t_D
4 * t_D
8* t_D 8* t_D
8* t_D
8* t_D
4*t_D
2*t_D
(P1 TRANSMIT)
8 * t_D
2µs
8 * t_D
8* t_D 8* t_D
8* t_D
8* t_D
12 * t_D
DAISY CHAIN DATA RESPONSE
t5
t5 = t_SPI  8 + t_LEAD + t_LAG + t_DRSP + t_CS + t_D  D  8 + 10 + N – 2 + 4s
Where:
t_SPI = SPI clock period
t_D = Daisy chain clock period
t_CS = Host delay from DATA READY to the first SPI clock
t_DRSP = CS High to DATA READY High
t_LEAD = CS Low to first SPI Clock
t_LAG = Last SPI Clock CS High
N = Stack position of top device
D = Number of bytes in response
FIGURE 76. RESPONSE TIMING (TOP DEVICE)
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FN8830.1
June 16, 2016