ISL78610 Datasheet, PDF (75/98 Pages) Intersil Corporation – Multi-Cell Li-Ion Battery Manager

ISL78610
Each device must receive a valid communications sequence
before its watchdog timeout period is exceeded. A valid
communications sequence is one that requires an action or
response from the device. Address All commands, such as the
Scan and Balance commands provide a simple way to reset the
watchdog timers on all devices with a single communication.
Single device communications (e.g., ACK) must be sent
individually to each device to reset the watchdog timer in that
device. A read of the Fault Status register of each device is also a
good way to reset the watchdog timer on each device. This
functionality guards against situations where a runaway host
microcontroller might continually send data.
Failure to receive valid communications within the required time
causes the WDGF bit to be set in the Fault Status register and the
device to be placed in Sleep mode, with all measurement and
balancing functions disabled. Daisy chain devices assert the FAULT
output in response to a watchdog fault and maintain this asserted
state while in Sleep mode. Notice that no watchdog fault response
is automatically sent on the daisy chain interface.
WATCHDOG FUNCTION
The watchdog timeout is settable in two ranges using the lower 7
bits of the Watchdog/Balance time register (see Table 45). The
low range (7’b0000001 to 7’b0111111) provides timeout
settings in 1 second increments from 1 second to 63 seconds.
The high range (7’b1000000 to 7’b1111111) provides timeout
settings in 2 minute intervals from 2 minutes to 128 minutes
(see Table 45 for details).
TABLE 45. WATCHDOG/BALANCE TIME REGISTER
REGISTER BITS
6
5
4
3
2
1
0
WATCHDOG
WDG6 WDG5 WDG4 WDG3 WDG2 WDG1 WDG0 TIMEOUT
0
0
0
0
0
0
0
Disabled
0
0
0
0
0
0
1
1s
0
0
0
0
0
1
0
2s
•••
-
0
1
1
1
1
1
0
62s
0
1
1
1
1
1
1
63s
1
0
0
0
0
0
0
2min
1
0
0
0
0
0
1
4min
•••
-
1
1
1
1
1
1
0
126min
1
1
1
1
1
1
1
128min
A zero setting (7’b0000000) disables the watchdog function. A
watchdog password function is provided to guard against
accidental disabling of the watchdog function. The upper 6 bits of
the Device Setup register must be set to 6’h3A (111010) to allow
the watchdog to be set to zero. The watchdog is disabled by first
writing the password to the Device Setup register (see “Set-Up
Registers” on page 87) and then writing zero to the lower bits of
the Watchdog/Balance time register. The password function
does not prevent changing the watchdog timeout setting to a
different nonzero value.
The watchdog continues to function when the ISL78610 is in
Sleep mode. Parts in Sleep mode assert the FAULT output when
the watchdog timer expires.
WATCHDOG PASSWORD
Before writing a zero to the watchdog timer, which turns off the
timer, it is necessary to write a password to the [WP5:0] bits. The
password value is 6’h3A.
Alarm Response
If any of the fault bits are set, the FAULT logic output is asserted
low in response to the fault condition. The output then remains
low until the bits of the Fault Status register are reset. Individual
bits in the fault data registers must first be cleared before the
associated bits in the Fault Status register can be cleared.
If the device is in a daisy chain, the Fault logic also sends an
“unprompted” response down the daisy chain to the master,
which notifies the host microcontroller that a problem exists.
The daisy chain fault response is immediate, so long as there is
no communications activity on the device ports, and comprises
the normal Fault Status register read response. As such, it
includes the contents of the Status Register and includes the
device address that is reporting the fault.
The Fault response is only sent for the first fault occurrence.
Subsequent faults do not activate the Fault response until after
the Fault Status register has been cleared. If multiple devices
report a fault, the response shows the results from the lowest
stack device.
If a fault occurs while the device ports are active, then the device
waits until communications activity ceases before sending the
Fault response. The host microcontroller has the option to wait
for this response before sending the next message. Alternately
the host microcontroller may send the next message
immediately (after allowing the daisy chain ports to clear – see
“Sequential Daisy Chain communications” on page 66). Any
conflicts resulting from additional transmissions from the stack
are recognized by the lack of response from the stack.
Table 46 provides the maximum time from DATA READY going
low for the last byte of the normal response to DATA READY going
low for the first byte of the Fault response in the case where a
Fault response is held up by active communications.
TABLE 46. MAXIMUM TIME BETWEEN DATA READY SIGNALS –
DELAYED FAULT RESPONSE
MAXIMUM TIME BETWEEN
DATA READY ASSERTIONS
DAISY CHAIN DATA RATE (kHz) 500 250 125 62.5 UNIT
Fault Response
68 136 272 544 µs
Further read communications to the device return the Fault
response followed by the requested data. Write communications
return only the Fault response. Action commands return nothing.
The host microcontroller resets the register bits corresponding to
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FN8830.1
June 16, 2016