VS28F016SV Datasheet, PDF (7/50 Pages) Intel Corporation – 16-Mbit (1-Mbit x 16, 2-Mbit x 8) FlashFileTM MEMORY

VS28F016SV MS28F016SV FlashFile^TM Memory
2 1 Lead Descriptions
Symbol
Type
A₀
INPUT
A₁ - A₁₅
INPUT
A₁₆ - A₂₀
INPUT
DQ₀ - DQ₇
INPUT OUTPUT
DQ₈ - DQ₁₅ INPUT OUTPUT
CE₀ CE₁
INPUT
RP
INPUT
OE
INPUT
WE
INPUT
Name and Function
BYTE-SELECT ADDRESS Selects between high and low byte when
device is in x8 mode This address is latched in x8 Data Writes Not
used in x16 mode (i e the A₀ input buffer is turned off when BYTE
is high)
WORD-SELECT ADDRESSES Select a word within one 64-Kbyte
block A_6-15 selects 1 of 1024 rows and A_1-5 selects 16 of 512
columns These addresses are latched during Data Writes
BLOCK-SELECT ADDRESSES Select 1 of 32 Erase blocks These
addresses are latched during Data Writes Erase and Lock-Block
operations
LOW-BYTE DATA BUS Inputs data and commands during CUI write
cycles Outputs array buffer identifier or status data in the
appropriate read mode Floated when the chip is de-selected or the
outputs are disabled
HIGH-BYTE DATA BUS Inputs data during x16 Data-Write
operations Outputs array buffer or identifier data in the appropriate
read mode not used for Status Register reads Floated when the
chip is de-selected or the outputs are disabled
CHIP ENABLE INPUTS Activate the device’s control logic input
buffers decoders and sense amplifiers With either CE₀ or CE₁
high the device is de-selected and power consumption reduces to
standby levels upon completion of any current Data-Write or Erase
operations Both CE₀ CE₁ must be low to select the device
All timing specifications are the same for both signals Device
Selection occurs with the latter falling edge of CE₀ or CE₁ The
first rising edge of CE₀ or CE₁ disables the device
RESET POWER-DOWN RP low places the device in a Deep
Power-Down state All circuits that consume static power even those
circuits enabled in standby mode are turned off When returning from
Deep Power-Down a recovery time of t_PHQV at 5 0V V_CC is required
to allow these circuits to power-up
When RP goes low any current or pending WSM operation(s) are
terminated and the device is reset All Status Registers return to
ready (with all status flags cleared)
Exit from Deep Power-Down places the device in read array mode
OUTPUT ENABLE Gates device data through the output buffers
when low The outputs float to tri-state off when OE is high
NOTE
CE_x overrides OE and OE overrides WE
WRITE ENABLE Controls access to the CUI Page Buffers Data
Queue Registers and Address Queue Latches WE is active low
and latches both address and data (command or array) on its rising
edge Page Buffer addresses are latched on the falling edge of WE
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