VS28F016SV Datasheet, PDF (15/50 Pages) Intel Corporation – 16-Mbit (1-Mbit x 16, 2-Mbit x 8) FlashFileTM MEMORY

VS28F016SV MS28F016SV FlashFile^TM Memory
NOTES
1 RA can be the GSR address or any BSR address See Figures 4 and 5 for Extended Status Register memory maps
2 Upon device power-up all BSR lock-bits come up locked The Upload Status Bits command must be written to reflect the
actual lock-bit status
3 A₀ is automatically complemented to load second byte of data BYTE must be at V_IL A₀ value determines which
WD BC is supplied first A₀ e 0 looks at the WDL BCL A₀ e 1 looks at the WDH BCH
4 BCH WCH must be at 00H for this product because of the 256-byte (128-word) Page Buffer size and to avoid writing the
Page Buffer contents to more than one 256-byte segment within an array block They are simply shown for future Page
Buffer expandability
5 In x16 mode only the lower byte DQ_0-7 is used for WCL and WCH The upper byte DQ_8-15 is a don’t care
6 PA and PD (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle which is not shown
7 This command allows the user to swap between available Page Buffers (0 or 1)
8 These commands reconfigure RY BY output to one of two pulse-modes or enable and disable the RY BY function
9 Write address WA is the Destination address in the flash array which must match the Source address in the Page Buffer
Refer to the 16-Mbit Flash Product Family User’s Manual
10 BCL e 00H corresponds to a byte count of 1 Similarly WCL e 00H corresponds to a word count of 1
11 After writing the Upload Device Information command and the Confirm command the following information is output at
Page Buffer addresses specified below
Address
Information
06H 07H (Byte Mode)
Device Revision Number
03H (Word Mode)
Device Revision Number
1EH (Byte Mode)
Device Configuration Code
0FH (DQ_0–7) (Word Mode)
1FH (Byte Mode)
Device Configuration Code
Device Proliferation Code (01H)
0FH (DQ_8–15) (Word Mode)
Device Proliferation Code (01H)
A page buffer swap followed by a page buffer read sequence is necessary to access this information The contents of
all other Page Buffer locations after the Upload Device Information command is written are reserved for future imple-
mentation by Intel Corporation See Section 4 8 for a description of the Device Configuration Code This code also
corresponds to data written to the 28F016SV after writing the RY BY Reconfiguration command
12 To ensure that the 28F0165V’s power consumption during Sleep Mode reaches the deep power-down current level the
system also needs to de-select the chip by taking either or both CE₀ or CE₁ high
13 The upper byte of the data bus (DQ_8–15) during command wntes is a Don’t Care in x16 operation of the device
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