VS28F016SV Datasheet, PDF (33/50 Pages) Intel Corporation – 16-Mbit (1-Mbit x 16, 2-Mbit x 8) FlashFileTM MEMORY

VS28F016SV MS28F016SV FlashFile^TM Memory
NOTES
1 See AC Input Output Reference Waveforms for timing measurements Figures 6 and 7
2 OE may be delayed up to t_ELQV – t_GLQV after the falling edge of CE without impacting t_ELQV
3 Sampled not 100% tested Guaranteed by design
4 Device speeds are defined as
80 85 100 ns at V_CC e 5 0V equivalent to
120 ns at V_CC e 3 3V
5 See the high speed AC Input Output Reference Waveforms and AC Testing Load Circuit
6 See the standard AC Input Output Reference Waveforms and AC Testing Load Circuit
7 CE_x is defined as the latter of CE₀ or CE₁ going low or the f
8 This timing parameter is used to latch the correct BSR data onto the outputs
9 The address setup requirement for Extended Status Register reads must only be met referenced to the falling edge of the
last control signal to become active (CE₀ CE₁ or OE ) For example if CE₀ or CE₁ are activated prior to OE for
an Extended Status Register read specification t_AVGL must be met On the other hand if either CE₀ or CE₁ (or both)
are activated after OE specification t_AVEL must be referenced
NOTE
CEx is defined as the latter of CE₀ or CE₁ going low or the first of CE₀ or CE₁ going high
Figure 11 Read Timing Waveforms
271312 – 11
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