VS28F016SV Datasheet, PDF (4/50 Pages) Intel Corporation – 16-Mbit (1-Mbit x 16, 2-Mbit x 8) FlashFileTM MEMORY

VS28F016SV MS28F016SV FlashFile^TM Memory
Writing of memory data is performed in either byte or
word increments typically within 6 msec (12 0V V_PP)
b _{a 33% improvement over the VE28F008 or}
M28F008 A Block Erase operation erases one of
the 32 blocks in about 1 0 sec (12 0V V_PP) indepen-
dent of the other blocks which is about a 65% im-
provement over the VE28F008 or M28F008
Each block can be written and erased a minimum of
100 000 cycles Systems can achieve one million
Block Erase Cycles by providing wear-leveling algo-
rithms and graceful block retirement These tech-
niques have already been employed in many flash
file systems and hard disk drive designs
The VS MS28F016SV incorporates two Page Buff-
ers of 256 bytes (128 words) each to allow page
data writes This feature can improve a system write
performance by up to 4 8 times over previous flash
memory devices which have no Page Buffers
All operations are started by a sequence of Write
commands to the device Three Status Registers
(described in detail later in this data sheet) and a
RY BY output pin provide information on the prog-
ress of the requested operation
While the VE28F008 or M28F008 requires an opera-
tion to complete before the next operation can be
requested the VS MS28F016SV allows queuing of
the next operation while the memory executes the
current operation This eliminates system overhead
when writing several bytes in a row to the array or
erasing several blocks at the same time The
VS MS28F016SV can also perform Write operations
to one block of memory while performing Erase of
another block
The VS MS28F016SV provides selectable block
locking to protect code or data such as Device Driv-
ers PCMCIA card information ROM-Executable
O S or Application Code Each block has an associ-
ated non-volatile lock-bit which determines the
lock status of the block In addition the
VS MS28F016SV has a master Write Protect pin
(WP ) which prevents any modifications to memory
blocks whose lock-bits are set
The VS MS28F016SV contains three types of
Status Registers to accomplish various functions
 A Compatible Status Register (CSR) which is
100% compatible with the VE28F008 or
M28F008 FlashFile memory Status Register The
CSR when used alone provides a straightfor-
ward upgrade capability to the VS MS28F016SV
from a VE28F008- or M28F008-based design
 A Global Status Register (GSR) which informs
the system of command Queue status Page
Buffer status and overall Write State Machine
(WSM) status
 32 Block Status Registers (BSRs) which provide
block-specific status information such as the
block lock-bit status
The GSR and BSR memory maps for Byte-Wide and
Word-Wide modes are shown in Figures 4 and 5
The VS MS28F016SV incorporates an open drain
RY BY output pin This feature allows the user to
OR-tie many RY BY pins together in a multiple
memory configuration such as a Resident Flash Ar-
ray
Other configurations of the RY BY pin are en-
abled via special CUI commands and are described
in detail in the 16-Mbit Flash Product Family User’s
Manual
The VS MS28F016SV’s Upload Device Information
command is enhanced compared to the VE28F008
or M28F008 providing access to additional device
information This command uploads the Device Re-
vision Number Device Proliferation Code and De-
vice Configuration Code The Device Proliferation
Code for the VS MS28F016SV is 01H and the De-
vice Configuration Code identifies the current
RY BY configuration Section 4 4 documents the
exact page buffer address locations for all uploaded
information A subsequent Page Buffer Swap and
Page Buffer Read command sequence is necessary
to read the correct device information
The VS MS28F016SV also incorporates a dual chip-
enable function with two input pins CE₀ and
CE₁ These pins have exactly the same functional-
ity as the regular chip-enable pin CE on the
VE28F008 or M28F008 For minimum chip designs
CE₁ may be tied to ground and system logic may
use CE₀ as the chip enable input The
VS MS28F016SV uses the logical combination of
these two signals to enable or disable the entire
chip Both CE₀ and CE₁ must be active low to
enable the device If either one becomes inactive
the chip will be disabled This feature along with the
open drain RY BY pin allows the system designer
to reduce the number of control pins used in a large
array of 16-Mbit devices
The BYTE pin allows either x8 or x16 read writes
to the VS MS28F016SV BYTE at logic low se-
lects 8-bit mode with address A₀ selecting between
low byte and high byte On the other hand BYTE
4