VS28F016SV Datasheet, PDF (14/50 Pages) Intel Corporation – 16-Mbit (1-Mbit x 16, 2-Mbit x 8) FlashFileTM MEMORY

VS28F016SV MS28F016SV FlashFile^TM Memory
4 4 VS MS28F016SV Performance Enhancement Command Bus Definitions
Command
Mode
Notes
First Bus Cycle
Second Bus Cycle
Third Bus Cycle
Oper Addr Data⁽¹³⁾ Oper Addr Data⁽¹³⁾ Oper Addr Data
Read Extended
Status Register
1
Write X
xx71H Read RA GSRD
BSRD
Page Buffer Swap
7
Write X
xx72H
Read Page Buffer
Write X
xx75H Read PA
PD
Single Load to
Page Buffer
Write X
xx74H Write PA
PD
Sequential Load to x8 4 6 10 Write X
Page Buffer
x16 4 5 6 10 Write X
xxE0H Write X
xxE0H Write X
BCL Write X
WCL Write X
BCH
WCH
Page Buffer Write
to Flash
x8 3 4 9 10 Write X
x16 4 5 10 Write X
xx0CH Write A₀ BC(L H) Write WA BC(H L)
xx0CH Write X
WCL Write WA WCH
Two-Byte Write
Lock Block
Confirm
x8
3
Write X
xxFBH Write A₀ WD(L H) Write WA WD(H L)
Write X
xx77H Write BA xxD0H
Upload Status
Bits Confirm
2
Write X
xx97H Write X
xxD0H
Upload Device
Information
Confirm
11
Write X
xx99H Write X
xxD0H
Erase All Unlocked
Blocks Confirm
Write X xxA7H Write X xxD0H
RY BY Enable to
Level-Mode
8
Write X
xx96H Write X
xx01H
RY BY Pulse-
On-Write
8
Write X
xx96H Write X
xx02H
RY BY Pulse-
On-Erase
8
Write X
xx96H Write X
xx03H
RY BY Disable
8
Write X
xx96H Write X
xx04H
RY BY Pulse-
On-Write Erase
8
Write X
xx96H Write X
xx05H
Sleep
12 Write X xxF0H
Abort
Write X
xx80H
ADDRESS
BA e Block Address
PA e Page Butter Address
RA e Extended Register Address
WA e Write Address
X e Don’t Care
DATA
AD e Array Data
PD e Page Buffer Data
BSRD e BSR Data
GSRD e GSR Data
WC (L H) e Word Count (Low High)
BC (L H) e Byte Count (Low High)
WD (L H) e Write Data (Low High)
14