VS28F016SV Datasheet, PDF (5/50 Pages) Intel Corporation – 16-Mbit (1-Mbit x 16, 2-Mbit x 8) FlashFileTM MEMORY

VS28F016SV MS28F016SV FlashFile^TM Memory
at logic high enables 16-bit operation with address
A₁ becoming the lowest order address and address
A₀ is not used (don’t care) A device block diagram
is shown in Figure 1
The VS MS28F016SV is specified for a maximum
access time of 80 ns (t_ACC) at 5 0V operation (4 75V
to 5 25V) in either the SE1 or SE2 grades A corre-
sponding maximum access time of 120 ns at 3 3V
(3 15V to 3 45V) is achieved for reduced power con-
sumption applications
The VS MS28F016SV incorporates an Automatic
Power Saving (APS) feature which substantially re-
duces the active current when the device is in static
mode of operation (addresses not switching) In APS
mode the typical I_CC current is 1 mA at 5 0V (0 8 mA
at 3 3V)
A deep power-down mode of operation is invoked
when the RP (called PWD on the VE28F008 or
M28F008) pin transitions low This mode brings the
device power consumption to less than 30 0 mA typ-
ically and provides additional write protection by
acting as a device reset pin during power transitions
A reset time of 500 ns (5 0V V_CC operation) is re-
quired from RP switching high until outputs are
again valid In the Deep Power-Down state the
WSM is reset (any current operation will abort) and
the CSR GSR and BSR registers are cleared
A CMOS standby mode of operation is enabled
when either CE₀ or CE₁ transitions high and
RP stays high with all input control pins at CMOS
levels In this mode the device typically draws an
I_CC standby current of 70 mA at 5V V_CC
2 0 DEVICE PINOUT
The VS MS28F016SV 56L-SSOP pinout configura-
tion is shown in Figure 2
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