VS28F016SV Datasheet, PDF (13/50 Pages) Intel Corporation – 16-Mbit (1-Mbit x 16, 2-Mbit x 8) FlashFileTM MEMORY

VS28F016SV MS28F016SV FlashFile^TM Memory
4 3 VE28F008 and M28F008 Compatible Mode Command Bus Definitions
Command
Notes
First Bus Cycle
Oper Addr Data⁽⁴⁾
Second Bus Cycle
Oper Addr Data⁽⁴⁾
Read Array
Write
X
xxFFH Read AA
AD
Intelligent Identiier
1
Write
X
xx90H Read
IA
ID
Read Compatible Status Register
2
Write
X
xx70H Read
X
CSRD
Clear Status Register
3
Write
X
xx50H
Word Byte Write
Write
X
xx40H Write WA
WD
Alternate Word Byte Write
Write
X
xx10H Write WA
WD
Block Erase Confirm
Write
X
xx20H Write BA xxD0H
Erase Suspend Resume
Write
X
xxB0H Write
X
xxD0H
ADDRESS
DATA
AA ^e Array Address
AD ^e Array Data
BA ^e Block Address
CSRD ^e CSR Data
IA ^e ldentitier Address ID ^e Identifier Data
WA ^e Write Address
WD ^e Write Data
NOTES
X ^e Don’t Care
1 Following the Intelligent Identifier command two Read operations access the manutacturer and device signature codes
2 The CSR is automatically available after device enters data write erase or suspend operations
3 Clears CSR 3 CSR 4 and CSR 5 Also clears GSR 5 and all BSR 5 BSR 4 and BSR 2 bits See Status Register defini-
tions
4 The upper byte of the data bus (DQ_8–15) during command writes is a ‘‘Don’t Care’’ in x16 operation of the device
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