915GM Datasheet, PDF (7/48 Pages) Intel Corporation – 915GM/PM/GME/GMS and 910GML/GMLE Express Chipset

Summary Tables of Changes
Steppings
No
915PM
915GM/GME
915GMS
910GML/GMLE Plans
ERRATA
C0 C1 C2 B1 C1 C2 C0 C1 C2 B1 C1 C2
1
X
X
X
X
X
X
2
X
X
X
X
X
X
3
X
X
X
X
X
X
4
X
X
X
X
X
X
5
X
X
X
X
X
X
X
X
X
X
X
6
X
X
X
X
X
X
X
X
X
X
X
7
X
X
X
X
X
X
8
X
X
X
X
X
X
9
X
X
X
X
X
X
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
Reported L0s Exit
Latency Is Not
Updated When PCI
Express* Is Not
Operating in
Common Clock Mode
GMCH Will Not
Identify Back to Back
Malformed Packets
The GMCH Is Limited
to Reporting
Poisoned TLPs
through Standard
PCI Error Status
Reporting Structures
Incorrect PCI
Express Lane
Transition after
Receiving Several
TS1 Packets
DMI Link Egress Port
Address Is Not
Programmable
DDR2 OCD
Nonfunctional
PCI Express Graphics
Initiated Snooped
Reads to Memory
That Are Fast
Dispatched Could
Result in Incorrect
Data Being Returned
PCI Express
Common Mode
Voltage Noise
Immediately
Following Receiver
Detect sequence
GMCH Does Not
Ignore a PCI Express
Null Packet
Specification Update
7