915GM Datasheet, PDF (43/48 Pages) Intel Corporation – 915GM/PM/GME/GMS and 910GML/GMLE Express Chipset

Documentation Changes
7.
Section 17.2.14 C0DRC0 – Channel 0 DRAM Controller Mode 0
The following register bit definition replaces the Mobile Intel® 915PM/GM/GME/GMS
and 910GML/GMLE Express Chipset EDS Volume 2.0 (Doc #17139); Section 17.2.14.
Section 17.2.14 C0DRC0—Channel 0 DRAM Controller
Mode 0
PCI Device:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
120h
40002801h
RO, R/W
32 bits
Bit
31:30
29
28
27:24
23:22
21:20
Access
&
Default
Description
RO
01 b
R/W
0b
R/W
0b
R/W
0h
R/W
00 b
R/W
00 b
Reserved
Initialization Complete (IC):
This bit is used for communication of software state between the memory
controller and the BIOS. BIOS sets this bit to 1 after initialization of the DRAM
memory array is complete.
Reserved
Active SDRAM Ranks:
Implementations may use this field to limit the maximum number of SDRAM
ranks that may be active at once.
0000: All ranks allowed to be in the active state
0001: One Rank
0010: Two Ranks
0011: Three Ranks
Others: Reserved.
If this field is set to a non-zero value, then bits CXDRT2(4:0) should be set to
the minimum value as described by the formula, else the system hangs.
Reserved
Reserved
Specification Update
43