915GM Datasheet, PDF (12/48 Pages) Intel Corporation – 915GM/PM/GME/GMS and 910GML/GMLE Express Chipset

Summary Tables of Changes
Number
1
2
3
4
5
6
7
8
DOCUMENTATION CHANGES
DRAM Enhanced Addressing Update
Section 5.2.15 C0DRC1 – Channel 0 DRAM Controller Mode 1
Section 5.2.31 DCC – DRAM Channel Control
Section 2.2.33 GCFGC – Graphics Clock Frequency and Gating Control
Section 5.2.12 C0DRT1 – Channel 0 DRAM Timing Register 1
Section 2.5.3 – LBKLT_CRTL Signal Description Update
Section 17.2.14 C0DRC0 – Channel 0 DRAM Controller Mode 0
Section 17.2.15 C0DRC1 – Channel 0 DRAM Controller Mode 1
§
12
Specification Update