915GM Datasheet, PDF (42/48 Pages) Intel Corporation – 915GM/PM/GME/GMS and 910GML/GMLE Express Chipset

Documentation Changes
Bit
Access
and
Default
Description
DRAM RASB to CASB Delay (tRCD):
This bit controls the number of clocks inserted between a row activate
command and a read or write command to that row.
Encoding DDR tRCD DDR2 tRCD
000:
2
R/W
6:4
001:
3
001 b
010:
4
2 clocks
3 clocks (DDR2 400)
4 clocks (DDR2 533)
011:
5
5 clocks
100 - 111: Reserved Reserved
NOTE: Only the above recommended DDR2 timing values have been
validated.
3
RO
Reserved
DRAM RASB Precharge (tRP):
This bit controls the number of clocks that are inserted between a row
precharge command and an activate command to the same rank.
Encoding DDR tRP
DDR2 tRP
000:
2
R/W
2:0
001:
3
001 b
010:
4
2 Clocks
3 Clocks (DDR2 400)
4 Clocks (DDR2 533)
011:
5
5 Clocks
100 - 111: Reserved
NOTE: Only the above recommended DDR2 timing values have been
validated.
6.
LBKLT_CRTL Signal Description Update
The LBKLT_CRTL signal description in Section 2.5.3 should be replaced with the
following:
LBKLT_CRTL
O
HVCMOS
Panel Backlight Brightness Control:
Panel brightness control.
This signal is also called VARY_BL in the CPIS specification and
is used as the PWM Clock input signal. The accuracy of the
PWM duty cycle of LBKLT_CRTL signal for any given value will
be within ±20 ns.
42
Specification Update