915GM Datasheet, PDF (25/48 Pages) Intel Corporation – 915GM/PM/GME/GMS and 910GML/GMLE Express Chipset

Errata
30.
Mobile Intel 915PM/GM/GME Express Chipset x1 False Detect
Problem:
915PM/GM/GME may falsely detect the presence of a PCIe endpoint while operating in
PCIe Low Power Mode.
• False detect may occur for 915PM/GM/GME systems supporting x1 only endpoints.
• False detect may occur on PCIe* lanes 1 through 15 for a graphics endpoint when
switching from x16 to x1.
Implication: Systems may become inoperable when an endpoint is operating in x1 mode.
• The scenario occurs because false detection of a PCIe endpoint occurs on one or
more lanes resulting in the GMCH’s PCIe interface erroneously entering and
looping continuously in Polling.Compliance.
• When an endpoint is operating in x1 mode, the scenario may occur at boot or
during any subsequent attempt to retrain the link.
Workaround: For systems requiring x1 PCIe link operation:
• Systems operating in x1 mode only: It is possible for system BIOS to contain a
workaround. Contact your Intel field representative for more details.
• Systems requiring run-time switching between x16 and x1 operation: A graphics
driver workaround has been defined. Please contact your graphic’s controller
vendor for driver status.
• Use the erratum title when contacting graphic’s controller vendor for driver
status.
• For questions pertaining to the erratum or workaround please contact your Intel
representative.
Status:
For the steppings affected, see the Summary Tables of Changes.
31.
Mobile Intel 915PM/GM/GME Express Chipset PCI Express
Ztx_diff_dc Impedance Violation
Problem: 915PM/GM violates the PCI Express Ztx_diff_dc max impedance specification.
Implication: None
• No failures have been observed due to the violation of the PCI Express Ztx_diff_dc
impedance specification.
• PCI Express Tx_eye signal integrity specifications are still met.
Workaround: None
Status:
For affected steppings, see the Summary Tables of Changes.
Specification Update
25