915GM Datasheet, PDF (44/48 Pages) Intel Corporation – 915GM/PM/GME/GMS and 910GML/GMLE Express Chipset

Documentation Changes
Bit
19:18
17
16
15
14
13:12
11
10:8
7
Access
&
Default
Description
RO
00 b
R/W
0b
R/W
0b
R/W
0b
RO
0b
R/W
10 b
RO
1b
R/W
000 b
RO
0b
Reserved
Reserved
Reserved
CMD Copy Enable:
In a single channel mode, the CMD pins (MA, BS, RAS, CAS, WE) on both
channels are driven and are physical copies of each other.
Setting this bit disables the CMD pins on channel B. Having the additional copy
of CMD pins helps reduce loading on these pins, since in a two SO-DIMM
system, each copy can be routed up to separate SO-DIMM. In a single DIMM
system, the second copy can be disabled to eliminate unnecessary toggling of
these pins.
If this bit needs to be set, BIOS should do that before memory init sequence.
This bit should not be set in a dual channel system
Reserved
Reserved
Reserved
Refresh Mode Select (RMS):
This field determines whether refresh is enabled and, if so, at what rate
refreshes will be executed.
000: Refresh disabled
001: Refresh enabled. Refresh interval 15.6 µs
010: Refresh enabled. Refresh interval 7.8 µs
Other: Reserved
Reserved
44
Specification Update