915GM Datasheet, PDF (34/48 Pages) Intel Corporation – 915GM/PM/GME/GMS and 910GML/GMLE Express Chipset

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2.
Section 5.2.15 C0DRC1 – Channel 0 DRAM Controller Mode 1
The following register bits definition replaces the Mobile Intel® 915 and 910 Express
Chipset Family of Products Datasheet, Section 5.2.15
5.2.15 C0DRC1––Channel 0 DRAM Controller Mode 1
PCI Device:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
124h
00000000h
RO, R/W
32 bits
Bit
Access
and
Default
Description
Swap Mode Enable:
R/W
0 = Swap mode disabled. Dram Address Map Follows the standard
31
address map described in the EDS.
0b
1 = Swap mode enabled. This bit can be enabled if all dimm are either
single sided or symmetrically populated.
R/W
Reserved
30
0b
Address Swap Mode:
R/W
29
0 = Swap Enabled for Bank Selects and Rank Selects.
00 b
1 = Swap Enabled for Bank Selects only.
34
Specification Update