915GM Datasheet, PDF (45/48 Pages) Intel Corporation – 915GM/PM/GME/GMS and 910GML/GMLE Express Chipset

Documentation Changes
Access
Bit
&
Default
Description
6:4
R/W
Mode Select (SMS):
000 b
These bits select the special operational mode of the DRAM interface. The
special modes are intended for initialization at power up.
000:
Post Reset state – When the GMCH exits reset (power-up or
otherwise), the mode select field is cleared to 000.
During any reset sequence, while power is applied and reset is active, the
GMCH deasserts all DRAM CLK and CKE signals. After internal reset is
deasserted, DRAM CLK and CKE signals remain deasserted until this
field is written to a value different than “000”. On this event, DRAM
CLKs are enabled and CKE signals remain deasserted for a minumum
of 35 ns before CKE signals are asserted.
During suspend, GMCH internal signal triggers DRAM controller to flush
pending commands and enter all ranks into Self-Refresh mode. As
part of resume sequence, GMCH will be reset – which will clear this bit
field to “000” and maintain all DRAM CLK and CKE signals deasserted.
After internal reset is deasserted, DRAM CLK and CKE signals remain
deasserted until this field is written to a value different than “000”. On
this event, DRAM CLKs are enabled and CKE signals remain
deasserted for a minumum of 35 ns before CKE signals are asserted.
During entry to other low power states (C3, S1), GMCH internal signal triggers
DRAM controller to flush pending commands and enter all ranks into
Self-Refresh mode. During exit to normal mode, GMCH signal triggers
DRAM controller to exit Self-Refresh and resume normal operation
without S/W involvement.
001:
NOP Command Enable – All CPU cycles to DRAM result in a NOP
command on the DRAM interface.
010:
All Banks Pre-charge Enable – All CPU cycles to DRAM result in an
“all banks precharge” command on the DRAM interface.
011:
Mode Register Set Enable – All CPU cycles to DRAM result in a
“mode register” set command on the DRAM interface. Host address
lines are mapped to DRAM address lines in order to specify the
command sent. Host address lines [12:3] are mapped to MA[9:0],
and HA[13] is mapped to MA[11].
101:
Reserved
110:
CBR Refresh Enable – In this mode all CPU cycles to DRAM result
in a CBR
cycle on the DRAM interface
111:
Normal operation
R/W
Reserved
3
0b
Specification Update
45