915GM Datasheet, PDF (19/48 Pages) Intel Corporation – 915GM/PM/GME/GMS and 910GML/GMLE Express Chipset

Errata
12.
E_SMERR Bit Set Incorrectly
Problem:
The E_SMERR bit may be incorrectly set when performing valid accesses to SMM
space.
Implication: If this bit is used by the SMI handler to determine cache line flushes, unnecessary
cache line flushes may occur when in SMM mode. A slight performance impact to the
SMI handler may result from unnecessary cache line flushes.
Workaround: None
Status:
For the steppings affected, see the Summary Tables of Changes.
13.
PCI Express* Lane 3 Bit Errors Occur on a Small Percentage of GMCH
B-1 Units on Certain Boards
Problem:
On systems with External Graphics, a small percentage of GMCH B-1 units may
experience bit-errors on PCI Express lane 3 on certain boards. To date, we have only
seen these bit errors on internal test (SV) boards at nominal core voltage (1.05 V).
Implication: A significant level of bit errors could lead to link retraining, link down, or hang
conditions. Intel is currently trying to understand the variables that affect the bit error
rate. All samples shipped outside of Intel have been screened for this issue and Intel
has not seen any system hangs with screened parts. PCI Express x16 Graphics not
supported on Mobile Intel 915GM/GME B1 stepping.
Workaround: None
Status:
For the steppings affected, see the Summary Tables of Changes.
14.
Pixel Discoloration Seen When Intel® Dual Frequency Graphics
Technology (DFGT) Is Enabled
Problem:
Pixel discoloration seen when Intel Dual Frequency Graphics Technology (Intel DFGT)
is enabled. Root caused to the internal render clocks getting misaligned during the
frequency switching.
Implication: Pixel discoloration seen on display.
Workaround: Disable the DFGT feature through VBT.
Status:
For the steppings affected, see the Summary Tables of Changes.
15.
System Hang with DDR-333 Memory When Intel^® Rapid Memory
Power Management Is Enabled during C2/C3/C4
Problem:
DDR333 systems may not exit self refresh state when memory self refresh is enabled
during C2/C3/C4.
Implication: System may hang.
Workaround: None.
Status:
For the steppings affected, see the Summary Tables of Changes.
Specification Update
19