915GM Datasheet, PDF (37/48 Pages) Intel Corporation – 915GM/PM/GME/GMS and 910GML/GMLE Express Chipset

Documentation Changes
4.
Section 7.2.33 GCFGC – Graphics Clock Frequency and Gating Control
The following register bits definition replaces the Mobile Intel® 915 and 910 Express
Chipset Family of Products Datasheet; Section 7.2.33
Section 7.2.33 GCFGC—Graphics Clock Frequency and
Gating Control
PCI Device
Function:
Address Offset
Default Value
Access:
Size:
2
0
F0h
0000h
RO, R/W
16 bits
Bit
Access
and
Default
Description
15
R/W
Graphics Display Clock Low Frequency Override (for 915GMS
only):
0b
0 = Do not use Graphics cdclk low frequency override
1 = Use Graphics cdclk = 152 MHz low frequency
NOTE: This bit is reserved for 915GM, 910GML and 910GMLE
14
R/W
Reserved
0b
13
R/W
GFX GVL Low Frequency Enable:
0b
0 = Do not Use GFX GVL low frequency target for Render Clock.
1 = Use GFX GVL low frequency target for Render Clock.
12
R/W
GFX GVL Low Frequency Target:
0b
0 = 133 MHz (Default Value)
1 = Reserved
11
R/W
Gate Core Render Clock (GCRC):
0b
0: Core render clock (crclk) is running
1: Core render clock (crclk) is gated
10
R/W
Asynchronously Change Core Render Clock (ACCRC):
0b
A 0 to 1 transition on this bit will immediately load new pre- and post-
divider values for the crclk and crx2clk. Writing 1 to 1, 1 to 0, and 0 to
0 have no effect.
Specification Update
37