915GM Datasheet, PDF (26/48 Pages) Intel Corporation – 915GM/PM/GME/GMS and 910GML/GMLE Express Chipset

Errata
32.
Mobile Intel 915PM/GM/GMS/GME and 910GML/GMLE Express
Chipset DRAM Clock to CKE Power-up Timing
Problem:
During memory power-up and initialization, the timing between DRAM clock
stabilization to CKE going high is observed to be minimum of 35 ns against the JEDEC
spec of 200 µs.
Implication: None. No functional failures have been observed.
• Intel has characterized the timing and shared the data with major DRAM suppliers.
Intel has determined and major DRAM suppliers agree that DRAM devices need
< 35 ns. This erratum should not cause memory-clock functionality or timing
related issues. Please refer to latest Intel DRAM spec Addendum for power-up and
initialization timing requirements available at
http://developer.intel.com/technology/memory/#Specs
Workaround: None.
Status:
For affected steppings, see the Summary Tables of Changes.
33.
Mobile Intel 915PM/GM/GMS/GME and 910GML/GMLE Express
Chipset SMRAM D_CLS Bit
Problem:
Data and stack which residing in Extended SMRAM (TSEG/HSEG) is inaccessible if
D_CLS bit (Bus 0, Device 0, Function 0, Register 9Dh, Bit 5) is set.
Implication: May result in system hang.
Workaround: It is possible for system BIOS to contain a workaround. Contact your Intel field
representative for more details.
Status:
No Fix. For steppings affected, see the Summary Tables of Changes.
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Specification Update