915GM Datasheet, PDF (47/48 Pages) Intel Corporation – 915GM/PM/GME/GMS and 910GML/GMLE Express Chipset

Documentation Changes
Bit
26:24
23:20
19:16
15:13
12
11
10
9
Access
&
Default
Description
R/W
000 b
RO
00 h
R/W
0h
RO
000 b
R/W
0b
R/W
0b
R/W
0b
RO
0b
Reserved
Reserved
CKE Tri-state Enable Per Rank:
Bit 16 corresponds to rank 0
Bit 17 corresponds to rank 1
Bit 18 corresponds to rank 2
Bit 19 corresponds to rank3
0 = CKE is not tri-stated.
1 = CKE is tri-stated. This is set only if the Rank is physically not
populated.
Reserved
CS# Tri-state Enable (CSBTRIEN):
When set to a 1, the DRAM controller will tri-state CS# when the
corresponding CKE is deasserted.
0:
Address Tri-state Disabled
1:
Address Tri-state Enabled
Address Tri-state Enable (ADRTRIEN):
When set to a 1, the DRAM controller will tri-state the MA, CMD, and CSB
(CSB if lines only when all CKEs are deasserted. CKEs deassert based on
Idle timer or max rank count control.
0:
Address Tri-state Disabled
1:
Address Tri-state Enabled
Reserved
Reserved
Specification Update
47