915GM Datasheet, PDF (23/48 Pages) Intel Corporation – 915GM/PM/GME/GMS and 910GML/GMLE Express Chipset

Errata
25.
Mobile Intel 915PM/GM/GMS/GME and 910GML/GMLE Express
Chipset Memory Refresh Queue
Problem:
When thermal based throttling is enabled, memory refresh commands get queued up
inside MCH/GMCH. As a result, MCH/GMCH may not perform memory refresh
commands at a frequency needed by memory devices. Thermal based throttling
happens only when either using the on-die memory thermal sensors or the external
thermal sensor.
Implication: When not enough refresh commands are issued to system memory to retain memory
content, data loss may occur. System is more susceptible to this issue when memory
devices approach temperature limit.
Workaround: It is possible for system BIOS to contain a workaround. Contact your Intel field
representative for more details.
Status:
For affected steppings, see the Summary Tables of Changes.
26.
Packet Dropped When Replay Timer Expires and Replay Is in Progress
Problem:
When a packet replay is in progress on the PCI Express Port, and if some but not all of
the packets to be replayed are acknowledged and the replay timer expires on the
same clock cycle as the replay start of the first unacknowledged packet, the next
packet in the replay buffer may be sent with an old sequence number. That packet is
seen by receiver side as a duplicate and subsequently dropped.
Note: This has only been reproduced in a synthetic test environment.
Implication: Anomalous behavior may result if all of the above conditions are met.
Workaround: None
Status:
For the steppings affected, see the Summary Tables of Changes.
27.
LOCK to non-DRAM Memory Flag (Register Dev 0, Fun 0, Offset C8, Bit
9) Is Getting Asserted
Problem:
A CPU lock cycle request is unintentionally being recognized as request to a non-
system memory destination.
Implication: The GMCH may incorrectly flag an error for a valid lock cycle that targets DRAM. A
System Error (SERR) may be generated if enabled by System BIOS.
Note: The default setting for ERRCMD[9] Bus 0 Device 0 Offset CAh is to
disable this reporting.
Workaround: Do not enable or change default setting of ERRCMD[9] Bus 0 Device 0 Offset CAh
(SERR reporting for Lock cycles to non-DRAM Memory)
Status:
For the steppings affected, see the Summary Tables of Changes.
Specification Update
23