915GM Datasheet, PDF (41/48 Pages) Intel Corporation – 915GM/PM/GME/GMS and 910GML/GMLE Express Chipset

Documentation Changes
Bit
16
15:11
10
9:8
7
Access
and
Default
R/W
0b
R/W
01100 b
RO
R/W
01 b
RO
Description
Pre-All to Activate Delay (tRPALL).
This is applicable only to 8 bank architectures.
Must be set to 1 if any Rank is populated with 8 bank device technology.
0: tRPALL = tRP
1: tRPALL = tRP + 1
Refresh Cycle Time (tRFC).
Refresh cycle time is measured from a Refresh command (REF) until the first
Activate command (ACT) to the same rank, required to perform a read or write.
DDR 2 tRFC spec
tRFC
256 Mb
512 Mb
1 Gb
DDR2 400
(5 ns)
DDR2 533
(3.75 ns)
75 ns =
15 clks
75 ns =
20 clks
105 ns =
21 clks
105 ns =
28 clks
127.5 ns =
26 clks
127.5 ns =
34clks
DDR 1 tRFC spec
tRFC
64 Mb -512 Mb
1 Gb
DDR 333 ^{75 ns = 13 clks}
(6 ns)
120 ns = 20 clks
00000b – 11111b Zero Clocks to Thirty-one Clocks respectively
Actual clocks period depends on DDR clock frequency.
BIOS should round up. If the required clock count exceeds as
allowed by this register, the bios should set this register to the
max value and set corresponding bits in SDBUP.
Reserved
CASB Latency (tCL):
This value is programmable on DDR 2 SO-DIMM’s. The value programmed here
must match the CAS Latency of every DDR 2 SO-DIMM in the system.
Encoding DDR CL
DDR2 CL
00:
3
5
01:
2.5
4 (DDR2 533)
10:
Reserved 3 (DDR2 400)
11:
Reserved Reserved
NOTE: Only the above recommended DDR2 timing values have been validated.
Reserved
Specification Update
41