915GM Datasheet, PDF (33/48 Pages) Intel Corporation – 915GM/PM/GME/GMS and 910GML/GMLE Express Chipset

Documentation Changes
Table 10-9 DRAM Device Configurations –Dual Channel Interleaved Mode
w/ Enh. Addr. Swap (0)
Technology
(Mb)
Row bits
Column bits
Bank bits
Width (b)
Rows
Columns
Banks
Page Size (KB)
Devices per
rank
Rank Size
(MB)
Depth (M)
Addr bits [n:0]
Available in
DDR
Available in
DDRII
Host Address
bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
256
13
9
2
16
8192
512
4
4
4
128
16
26
yes
yes
-
-
-
r3
r 10
r9
r8
r7
r6
r5
r4
s0
b1
r1
r0
r 11
r 12
256 512 512 512
512
1024
13
10
2
8
8192
1024
4
8
13
10
2
16
8192
1024
4
8
13
11
2
8
8192
2048
4
16
13
10
2
16
8192
1024
4
8
14
10
2
8
16384
1024
4
8
14
10
2
16
16384
1024
4
8
8
4
8
4
8
4
256 256 512 256
512
512
32
32
64
32
64
64
27
27
28
27
28
28
yes yes yes
no
no
yes
yes
no
no
yes
yes
no
-
-
r3
r 12
r 10
r9
r8
r7
r6
r5
r4
s0
b1
r1
r0
r 11
r2
-
-
r3
r 12
r 10
r9
r8
r7
r6
r5
r4
s0
b1
r1
r0
r 11
r2
-
r3
r 11
r 12
r 10
r9
r8
r7
r6
r5
r4
s0
b1
r1
r0
r2
b0
Mem Addr-bit
-
-
r3
r 12
r 10
r9
r8
r7
r6
r5
r4
s0
b1
r1
r0
r 11
r2
-
r3
r 13
r 12
r 10
r9
r8
r7
r6
r5
r4
s0
b1
r1
r0
r 11
r2
-
r3
r 13
r 12
r 10
r9
r8
r7
r6
r5
r4
s0
b1
r1
r0
r 11
r2
1024
14
11
2
8
16384
2048
4
16
8
1024
128
29
Yes
No
r3
r 13
r 11
r 12
r 10
r9
r8
r7
r6
r5
r4
s0
b1
r1
r0
r2
b0
1024
13
10
3
16
8192
1024
8
8
4
512
64
28
no
yes
-
r3
r 11
r 12
r 10
r9
r8
r7
r6
b2
r4
s0
b1
r1
r0
r5
r2
1024
14
10
3
8
16384
1024
8
8
8
1024
128
29
no
yes
r3
r 13
r 11
r 12
r 10
r9
r8
r7
r6
b2
r4
s0
b1
r1
r0
r5
r2
Specification Update
33